-module EVAL(input clk, input mclk, input [7:0] Ein, output [7:0] Eout, output [3:0] gcop, output [5:0] ostate, input conn_ea, input conn_et);
+module EVAL(input clk, input clk_enable, input rst, input [15:0] Ein, output [15:0] Eout, output [3:0] gcop, output [5:0] ostate, input conn_ea, input conn_et);
reg [21:0] rom_output;
- reg [5:0] eostate = 6'o0;
+ reg [5:0] eostate;
reg [5:0] enstate;
- reg [7:0] Ein_latched;
+ reg [15:0] Ein_latched;
always @(posedge clk) begin
- Ein_latched <= Ein;
+ if(clk_enable) begin
+ Ein_latched <= Ein;
+ end
end
wire et_lit = rom_output[21];
wire ldN = rom_output[9];
wire ldX = rom_output[8];
wire ldV = rom_output[7];
- wire [3:0] gcop = rom_output[6:3];
+ assign gcop = rom_output[6:3];
wire [2:0] lit = rom_output[2:0];
+ wire et_zero = ~|E[15:13];
+ wire ea_zero = ~|E[12:0];
+
always @* begin
case(eostate)
6'o00: begin rom_output <= 22'o14004002; enstate <= 6'o01; end
end // always @ *
always @ (posedge clk) begin
- eostate <=
- et_disp ? (enstate | E[7:5]) :
- eaz_etz_eqv_disp ? (enstate | {ea_zero, et_zero, 1'b0}) :
- enstate;
+ if (rst)
+ eostate = 0;
+ if (clk_enable) begin
+ eostate <=
+ et_disp ? (enstate | E[15:13]) :
+ eaz_etz_eqv_disp ? (enstate | {ea_zero, et_zero, 1'b0}) :
+ enstate;
+ end
end
assign ostate = eostate;
- reg [7:0] V;
- reg [7:0] X;
- reg [7:0] N;
- reg [7:0] L;
- reg [7:0] C;
+ reg [15:0] V;
+ reg [15:0] X;
+ reg [15:0] N;
+ reg [15:0] L;
+ reg [15:0] C;
- wire [7:0] E;
+ wire [15:0] E;
- wire [7:0] EfromV = rdV ? V : 0;
- wire [7:0] EfromX = rdX ? X : 0;
- wire [7:0] EfromXp = rdXp ? {X[7:5], X[4:0] + 1} : 0;
- wire [7:0] EfromN = rdN ? N : 0;
- wire [7:0] EfromL = rdL ? L : 0;
- wire [7:0] EfromC = rdC ? C : 0;
- wire [4:0] EAfromEin = conn_ea ? Ein[4:0] : 0;
- wire [3:0] ETfromEin = conn_et ? Ein[7:5] : 0;
- wire [7:0] EfromEin = {ETfromEin, EAfromEin};
- wire [4:0] EAfromLIT = ea_lit ? {1'b0, lit, 1'b0} : 0;
- wire [3:0] ETfromLIT = et_lit ? lit : 0;
- wire [7:0] EfromLIT = {ETfromLIT, EAfromLIT};
+ wire [15:0] EfromV = rdV ? V : 0;
+ wire [15:0] EfromX = rdX ? X : 0;
+ wire [15:0] EfromXp = rdXp ? {X[15:13], X[12:0] + 1} : 0;
+ wire [15:0] EfromN = rdN ? N : 0;
+ wire [15:0] EfromL = rdL ? L : 0;
+ wire [15:0] EfromC = rdC ? C : 0;
+ wire [12:0] EAfromEin = conn_ea ? Ein[12:0] : 0;
+ wire [2:0] ETfromEin = conn_et ? Ein[15:13] : 0;
+ wire [15:0] EfromEin = {ETfromEin, EAfromEin};
+ wire [12:0] EAfromLIT = ea_lit ? {8'b0, lit, 1'b0} : 0;
+ wire [2:0] ETfromLIT = et_lit ? lit : 0;
+ wire [15:0] EfromLIT = {ETfromLIT, EAfromLIT};
assign E = EfromV | EfromX | EfromXp | EfromN | EfromL | EfromC | EfromLIT | EfromEin;
assign Eout = EfromV | EfromX | EfromXp | EfromN | EfromL | EfromC | EfromLIT;
always @ (posedge clk) begin
- if (ldV) V <= E;
- if (ldX) X <= E;
- if (ldN) N <= E;
- if (ldL) L <= E;
- if (ldC) C <= E;
+ if (clk_enable) begin
+ if (ldV) V <= E;
+ if (ldX) X <= E;
+ if (ldN) N <= E;
+ if (ldL) L <= E;
+ if (ldC) C <= E;
+ end
end
endmodule // EVAL