-`include "ram.v"
-`include "chip.v"
-`include "uart.v"
+`include "master.v"
+`include "worker.v"
-module toplevel (input CLKin, output [4:0] led, output uart_tx, input uart_rx);
- wire clk = CLKin;
+module toplevel (input CLKin, output [4:0] led);
+ wire worker_tx;
+ wire worker_rx;
- wire [11:0] mem_addr;
- wire [15:0] mem_in;
- wire [15:0] mem_out;
- wire mem_write;
+ wire worker_ready;
+ wire master_ready;
- RAM #(.ADDRESS_BITS(12)) ram (.clk(clk), .write(mem_write), .addr(mem_addr), .in(mem_in), .out(mem_out));
+ wire [4:0] worker_led;
+ wire [4:0] master_led;
- reg [7:0] from_uart [3:0];
- reg [2:0] uart_ptr = 0;
+ worker worker (.CLKin(CLKin), .led(worker_led), .uart_tx(worker_tx), .uart_rx(worker_rx), .ready_out(worker_ready), .ready_in(master_ready));
- wire [15:0] I = {from_uart[1], from_uart[0]};
- assign mem_addr = from_uart[2];
- wire [2:0] op_from_uart = from_uart[3][2:0];
- wire CS = from_uart[3][3];
+ master master (.CLKin(CLKin), .led(master_led), .uart_tx(worker_rx), .uart_rx(worker_tx), .ready_out(master_ready), .ready_in(worker_ready));
- reg [2:0] op = 0;
-
- assign led = uart_ptr;
-
- chip chip (.clk(clk), .op(op), .I(I), .io_pin(0), .CS(CS), .mem_in(mem_in), .mem_out(mem_out), .mem_write(mem_write));
-
- wire received;
- wire [7:0] rx_byte;
- reg transmit = 0;
- reg [7:0] tx_byte;
-
- uart uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .received(received), .transmit(transmit), .tx_byte(tx_byte), .rx_byte(rx_byte));
-
- reg [15:0] rom_I [0:5];
- reg [7:0] rom_mem_addr [0:5];
- reg [2:0] rom_op [0:5];
- reg rom_CS [0:5];
-
- reg [2:0] state = 0;
-
- always @ (posedge clk) begin
- if (received) begin
- from_uart[uart_ptr] <= rx_byte;
- uart_ptr <= uart_ptr + 1;
- end
-
- if (uart_ptr == 4) begin
- op <= op_from_uart;
- uart_ptr <= 0;
- state <= 1;
- end
-
- if (state == 1) begin
- transmit <= 1;
- tx_byte <= mem_in;
- state <= 2;
- end
-
- if (state == 2) begin
- transmit <= 0;
- state <= 0;
- end
-
- if (op != 0) begin
- op <= 0;
- end
- end
+ assign led = worker_led | master_led;
endmodule