-module WRITER (input clk, input clk_enable, output [7:0] uart_tx_byte, output reg uart_tx_signal = 0, input uart_is_transmitting, output reg finished = 0, input [15:0] result);
- reg [2:0] state = `STATE_WRITE_TYPE;
- reg [3:0] tx_hex = 0;
+module WRITER (input clk, input clk_enable, output [7:0] tx_byte, output tx_signal, input tx_busy, output finished, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] freeptr);
+ reg [2:0] state = `STATE_START;
+ reg [12:0] current_index;