-PROJ = flash
-PIN_DEF = flash.pcf
+PROJ = toplevel
+PIN_DEF = toplevel.pcf
DEVICE = hx1k
all: $(PROJ).rpt $(PROJ).bin
%.blif: %.v
- yosys -p 'synth_ice40 -top top -blif $@' $<
+ tools/yosys/yosys -p 'synth_ice40 -top toplevel -blif $@' $<
%.asc: $(PIN_DEF) %.blif
- arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P tq144
+ tools/arachne-pnr/bin/arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P tq144
%.bin: %.asc
- icepack $< $@
+ tools/icestorm/icepack/icepack $< $@
%.rpt: %.asc
- icetime -d $(DEVICE) -mtr $@ $<
+ tools/icestorm/icetime/icetime -C tools/icestorm/icebox/chipdb-$(subst hx,,$(subst lp,,$(DEVICE))).txt -d $(DEVICE) -mtr $@ $<
prog: $(PROJ).bin
- iceprog $<
+ tools/icestorm/iceprog/iceprog $<
clean:
rm -f $(PROJ).blif $(PROJ).asc $(PROJ).bin
-.PHONY: all prog clean
+
+sim:
+ tools/yosys/yosys -p 'read_verilog -sv -DSIM toplevel.v; prep -top toplevel -nordff; sim -clock CLKin -vcd test.vcd -n 3000'
+
+.PHONY: all prog clean sim