Implement a tiny part of i2c

[clump.git] / Makefile

diff --git a/Makefile b/Makefile
index f26533bba3426cf418bfe3c80175a1945bed6e16..e2c55e51e8aeba470fb0bc42aa38029f57958b53 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,25 +1,29 @@
-PROJ = flash
-PIN_DEF = flash.pcf
+PROJ = master
+PIN_DEF = master.pcf
 DEVICE = hx1k
 
 all: $(PROJ).rpt $(PROJ).bin
 
 %.blif: %.v
-       yosys -p 'synth_ice40 -top top -blif $@' $<
+       tools/yosys/yosys -p 'synth_ice40 -top master -blif $@' $<
 
 %.asc: $(PIN_DEF) %.blif
-       arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P vq100
+       tools/arachne-pnr/bin/arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P tq144
 
 %.bin: %.asc
-       icepack $< $@
+       tools/icestorm/icepack/icepack $< $@
 
 %.rpt: %.asc
-       icetime -d $(DEVICE) -mtr $@ $<
+       tools/icestorm/icetime/icetime -C tools/icestorm/icebox/chipdb-$(subst hx,,$(subst lp,,$(DEVICE))).txt -d $(DEVICE) -mtr $@ $<
 
 prog: $(PROJ).bin
-       ./iCEburn.py  -e -v -w  $<
+       tools/icestorm/iceprog/iceprog $<
 
 clean:
        rm -f $(PROJ).blif $(PROJ).asc $(PROJ).bin
 
-.PHONY: all prog clean
+
+sim:
+       tools/yosys/yosys -p 'read_verilog -sv -DSIM master.v; prep -top master -nordff; sim -clock CLKin -vcd test.vcd -n 3000'
+
+.PHONY: all prog clean sim