`define GCOP_RDQCDRRX 4'd15
module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
- wire [7:0] result;
+ wire [15:0] result;
+
+ reg [5:0] initial_reset = 30;
+ always @ (posedge clk)
+ if (initial_reset) initial_reset <= initial_reset - 1;
reg [1:0] counter = 0;
- reg gc_clock = counter[1];
- wire eval_clock = !counter[1] & step_eval;
+ wire gc_clock_enable = counter[0] & counter[1] & !initial_reset;
+ wire eval_clock_enable = counter[0] & !counter[1] & step_eval & !initial_reset;
always @ (posedge clk)
counter <= counter + 1;
- wire [7:0] E1;
- wire [7:0] E2;
+ wire [15:0] E1;
+ wire [15:0] E2;
wire [3:0] gcop;
wire [5:0] gostate;
wire [5:0] eostate;
wire step_eval;
- GC gc (.clk(gc_clock), .mclk(clk), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .result(result));
+ wire ram_we;
+ wire [12:0] ram_addr;
+ wire [15:0] ram_di;
+ wire [15:0] ram_do;
+
+ GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do), .result(result));
+
+ GC gc (.clk(clk), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(ram_we), .ram_addr(ram_addr), .ram_di(ram_di), .ram_do(ram_do));
- EVAL eval (.clk(eval_clock), .mclk(clk), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
+ EVAL eval (.clk(clk), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
// UART outputs
wire uart_rx_signal;
// UART logic
reg uart_tx_signal = 1;
- wire [7:0] uart_tx_byte = result;
+ wire [7:0] uart_tx_byte = result[7:0];
// 300 baud uart
uart #(.CLOCK_DIVIDE(39)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));