+`include "pll.v"
`include "gc.v"
`include "eval.v"
`include "reader.v"
`ifdef SIM
`define UART_DIVIDE 1
`else
- `define UART_DIVIDE 625
+ `define UART_DIVIDE 3
`endif
-module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
+module cpu (input CLKin, output [4:0] led, output uart_tx, input uart_rx);
+ wire clk;
+
+ pll pll (.clock_in(CLKin), .clock_out(clk));
+
wire [12:0] freeptr;
wire [15:0] E1;
wire [15:0] E2;
GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do));
- GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .freeptr(freeptr));
+ GC gc (.clk(clk), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .freeptr(freeptr));
EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et), .eval_finished(eval_finished));
wire uart_tx_signal;
wire [7:0] uart_tx_byte;
- // 4800 baud uart
+ // 19200 baud uart
uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
endmodule