-`include "asciihex.v"
-`include "generic_fifo_sc_a.v"
`include "gc.v"
`include "eval.v"
-`include "ram.v"
`include "reader.v"
-`include "rom.v"
-`include "prescaler.v"
-`include "single_trigger.v"
`include "uart.v"
`include "writer.v"
`define UART_DIVIDE 625
`endif
-module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
+module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
wire [15:0] result;
reg [5:0] initial_reset = 30;
EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
- READER reader (.clk(clk), .clk_enable(!initial_reset), .uart_rx_byte(uart_rx_byte), .uart_rx_signal(uart_rx_signal), .uart_is_receiving(uart_is_receiving), .active(reader_active), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
+ READER reader (.clk(clk), .clk_enable(!initial_reset), .rx_byte(uart_rx_byte), .rx_signal(uart_rx_signal), .active(reader_active), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
- WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .uart_tx_byte(uart_tx_byte), .uart_tx_signal(uart_tx_signal), .uart_is_transmitting(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .P(P));
+ WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .tx_byte(uart_tx_byte), .tx_signal(uart_tx_signal), .tx_busy(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .P(P));
// UART outputs
wire uart_rx_signal;