X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=Makefile;h=0fb0a575be3498fa5c8ebb7dc58637598ad34449;hb=3b542afc856d736dfd2ff0eed081f647de07af4c;hp=df0855a93bc98b0a7a906b34742d26c8e3d39b4b;hpb=eba9336246cb6b2ec09c104a79ef43f8bfc30250;p=clump.git

diff --git a/Makefile b/Makefile
index df0855a..0fb0a57 100644
--- a/Makefile
+++ b/Makefile
@@ -1,11 +1,11 @@
-PROJ = lisp_processor
-PIN_DEF = lisp_processor.pcf
+PROJ = toplevel
+PIN_DEF = toplevel.pcf
 DEVICE = hx1k
 
 all: $(PROJ).rpt $(PROJ).bin
 
 %.blif: %.v
-	tools/yosys/yosys -p 'synth_ice40 -top cpu -blif $@' $<
+	tools/yosys/yosys -p 'synth_ice40 -top toplevel -blif $@' $<
 
 %.asc: $(PIN_DEF) %.blif
 	tools/arachne-pnr/bin/arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P tq144
@@ -22,4 +22,8 @@ prog: $(PROJ).bin
 clean:
 	rm -f $(PROJ).blif $(PROJ).asc $(PROJ).bin
 
-.PHONY: all prog clean
+
+sim:
+	tools/yosys/yosys -p 'read_verilog -sv -DSIM toplevel.v; prep -top toplevel -nordff; sim -clock CLKin -vcd test.vcd -n 3000'
+
+.PHONY: all prog clean sim