X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=Makefile;h=e2c55e51e8aeba470fb0bc42aa38029f57958b53;hb=ffba35f814eda0a4c47af601206cf2d3ab6eab03;hp=0fb0a575be3498fa5c8ebb7dc58637598ad34449;hpb=7f1b6bd9e0070ddc074215defc46d64abef645ac;p=clump.git

diff --git a/Makefile b/Makefile
index 0fb0a57..e2c55e5 100644
--- a/Makefile
+++ b/Makefile
@@ -1,11 +1,11 @@
-PROJ = toplevel
-PIN_DEF = toplevel.pcf
+PROJ = master
+PIN_DEF = master.pcf
 DEVICE = hx1k
 
 all: $(PROJ).rpt $(PROJ).bin
 
 %.blif: %.v
-	tools/yosys/yosys -p 'synth_ice40 -top toplevel -blif $@' $<
+	tools/yosys/yosys -p 'synth_ice40 -top master -blif $@' $<
 
 %.asc: $(PIN_DEF) %.blif
 	tools/arachne-pnr/bin/arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P tq144
@@ -24,6 +24,6 @@ clean:
 
 
 sim:
-	tools/yosys/yosys -p 'read_verilog -sv -DSIM toplevel.v; prep -top toplevel -nordff; sim -clock CLKin -vcd test.vcd -n 3000'
+	tools/yosys/yosys -p 'read_verilog -sv -DSIM master.v; prep -top master -nordff; sim -clock CLKin -vcd test.vcd -n 3000'
 
 .PHONY: all prog clean sim