X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=Makefile;h=e2c55e51e8aeba470fb0bc42aa38029f57958b53;hb=ffba35f814eda0a4c47af601206cf2d3ab6eab03;hp=7d80540cdc632d0d3582b21cb7f2b94fe80fcdea;hpb=7560fdba316d8bb53b01ee60eddc6581ff167c27;p=clump.git

diff --git a/Makefile b/Makefile
index 7d80540..e2c55e5 100644
--- a/Makefile
+++ b/Makefile
@@ -1,11 +1,11 @@
-PROJ = flash
-PIN_DEF = flash.pcf
+PROJ = master
+PIN_DEF = master.pcf
 DEVICE = hx1k
 
 all: $(PROJ).rpt $(PROJ).bin
 
 %.blif: %.v
-	tools/yosys/yosys -p 'synth_ice40 -top top -blif $@' $<
+	tools/yosys/yosys -p 'synth_ice40 -top master -blif $@' $<
 
 %.asc: $(PIN_DEF) %.blif
 	tools/arachne-pnr/bin/arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P tq144
@@ -22,4 +22,8 @@ prog: $(PROJ).bin
 clean:
 	rm -f $(PROJ).blif $(PROJ).asc $(PROJ).bin
 
-.PHONY: all prog clean
+
+sim:
+	tools/yosys/yosys -p 'read_verilog -sv -DSIM master.v; prep -top master -nordff; sim -clock CLKin -vcd test.vcd -n 3000'
+
+.PHONY: all prog clean sim