X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=chip.v;h=1ff0d50022a41d9918f528bffdb736e5379e5a9f;hb=7f1b6bd9e0070ddc074215defc46d64abef645ac;hp=b29fde674e49645d41ad06993427028e448a4612;hpb=3b542afc856d736dfd2ff0eed081f647de07af4c;p=clump.git

diff --git a/chip.v b/chip.v
index b29fde6..1ff0d50 100644
--- a/chip.v
+++ b/chip.v
@@ -1,13 +1,13 @@
 `include "news.v"
 
-`define OP_NOP   3'd0
-`define OP_LOADA 3'd1
-`define OP_LOADB 3'd2
-`define OP_STORE 3'd3
-`define OP_READ  3'd4
-`define OP_LOADI 3'd5
-`define OP_ROUTE 3'd6
-`define OP_RUG   3'd7
+`define OP_NOP    3'd0
+`define OP_LOADA  3'd1
+`define OP_LOADB  3'd2
+`define OP_STORE  3'd3
+`define OP_STOREI 3'd4
+`define OP_LOADI  3'd5
+`define OP_ROUTE  3'd6
+`define OP_LED    3'd7
 
 `define DIRECTION_N  3'd0
 `define DIRECTION_NE 3'd1
@@ -18,7 +18,7 @@
 `define DIRECTION_W  3'd6
 `define DIRECTION_NW 3'd7
 
-module chip(input clk, input [2:0] op, input [15:0] I, input io_pin, input CS, output reg [63:0] mem_in, input [63:0] mem_out, output reg mem_write);
+module chip(input clk, input [2:0] op, input [15:0] I, input io_pin, input CS, output reg [15:0] mem_in, input [15:0] mem_out, output reg mem_write, output reg [3:0] led_out = 0);
 
    // parity is unimplemented
 
@@ -50,29 +50,34 @@ module chip(input clk, input [2:0] op, input [15:0] I, input io_pin, input CS, o
    wire 	  news = I[2];
    wire [4:0] reg_ = I[8:4];
 
+   // OP_LED
+   wire 	  mode   = I[4];
+   wire [1:0] offset = I[1:0];
+   wire [3:0] leds   = I[3:0];
 
-   reg [63:0] A = 0;
-   reg [63:0] B = 0;
-   reg [63:0] C = 0;
-   reg [63:0] F = 0;
-   reg [63:0] Cond = 0;
-   reg [63:0] R = 0;
+
+   reg [15:0] A = 0;
+   reg [15:0] B = 0;
+   reg [15:0] C = 0;
+   reg [15:0] F = 0;
+   reg [15:0] Cond = 0;
+   reg [15:0] R = 0;
    reg [7:0]  alu_sum = 0;
    reg [7:0]  alu_carry = 0;
-   reg [63:0] cube_in;
+   reg [15:0] cube_in;
    reg 		  io;
 
    // these are not really regs
 
-   reg [63:0]  alu_sum_out;
-   reg [63:0]  alu_carry_out;
+   reg [15:0]  alu_sum_out;
+   reg [15:0]  alu_carry_out;
 
-   reg [2:0]  alu_index [63:0];
+   reg [2:0]  alu_index [15:0];
 
    reg [15:0]  idx;
 
    always @* begin
-	  for(idx = 0; idx < 64; idx=idx+1) begin
+	  for(idx = 0; idx < 16; idx=idx+1) begin
 		 alu_index[idx] = (A[idx] << 2) + (B[idx] << 1) + F[idx];
 		 alu_sum_out[idx] <= alu_sum[alu_index[idx]];
 		 alu_carry_out[idx] <= alu_carry[alu_index[idx]];
@@ -98,16 +103,16 @@ module chip(input clk, input [2:0] op, input [15:0] I, input io_pin, input CS, o
 		endcase
    end // always @ *
 
-   reg  [63:0] flags_in;
-   wire [63:0] flags_out;
+   reg  [15:0] flags_in;
+   wire [15:0] flags_out;
    reg 		   flags_write;
 
-   reg [63:0]  latest_news;
+   reg [15:0]  latest_news;
 
    RAM #(.ADDRESS_BITS(3)) flags (.clk(clk), .write(flags_write), .addr(flags_addr[2:0]), .in(flags_in), .out(flags_out));
 
-   reg [63:0]  flag_or_news;
-   reg [63:0]  news_out;
+   reg [15:0]  flag_or_news;
+   reg [15:0]  news_out;
 
    news newspaper (.news_in(latest_news), .direction(flags_addr[1:0]), .news_out(news_out));
 
@@ -145,7 +150,7 @@ module chip(input clk, input [2:0] op, input [15:0] I, input io_pin, input CS, o
 
 		`OP_STORE:
 		  begin
-			 for(idx = 0; idx < 64; idx++) begin
+			 for(idx = 0; idx < 16; idx++) begin
 				flags_in[idx] = Cond[idx] ? alu_carry_out[idx] : flags_out[idx];
 				latest_news[idx] <= flags_in[idx];
 			 end
@@ -157,18 +162,33 @@ module chip(input clk, input [2:0] op, input [15:0] I, input io_pin, input CS, o
 			 mem_write <= 1;
 		  end
 
-		`OP_READ:
+		`OP_STOREI:
 		  begin
-			 if (CS)
-			   mem_in <= mem_out;
+			 mem_in <= I;
+			 mem_write <= 1;
 		  end
-
+/*
 		`OP_LOADI:
 		  begin
 			 C <= mem_out;
 			 A <= I;
 			 alu_sum <= 8'b11110000; // out of A, B, F, select exactly A
 		  end
+*/
+
+		`OP_LED:
+		  begin
+			 if(!mode)
+			   led_out <= leds;
+			 else if(offset == 0)
+			   led_out <= mem_out[3:0];
+			 else if(offset == 1)
+			   led_out <= mem_out[7:4];
+			 else if(offset == 2)
+			   led_out <= mem_out[11:8];
+			 else if(offset == 3)
+			   led_out <= mem_out[15:12];
+		  end
 
 /*		`OP_RUG:
 		  begin