X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=eval.v;h=96cb68e2c8e865bf1da65449121c60a60495a775;hb=62e5ccb8304550f88f658af70a683936d47c08b2;hp=355a9ffef22379193b675d792e143f071c0a4200;hpb=5284821b41df368b5aa571f6ddd2440cfc2a6426;p=yule.git

diff --git a/eval.v b/eval.v
index 355a9ff..96cb68e 100644
--- a/eval.v
+++ b/eval.v
@@ -2,13 +2,10 @@ module EVAL(input clk, input clk_enable, input rst, input [15:0] Ein, output [15
    reg [21:0] rom_output;
    reg [5:0]  eostate;
    reg [5:0]  enstate;
-   reg [15:0]  Ein_latched;
 
-   always @(posedge clk) begin
-	  if(clk_enable) begin
-		 Ein_latched <= Ein;
-	  end
-   end
+`ifdef SIM
+   initial eostate <= 0;
+`endif
 
    wire et_lit = rom_output[21];
    wire ea_lit = rom_output[20];