X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=eval.v;h=96cb68e2c8e865bf1da65449121c60a60495a775;hb=62e5ccb8304550f88f658af70a683936d47c08b2;hp=8aa21590ca0ea88af0f0667a3b4db5b14f1dcddc;hpb=b5efed3aa26a11e1da3639806afea5c772fff7aa;p=yule.git

diff --git a/eval.v b/eval.v
index 8aa2159..96cb68e 100644
--- a/eval.v
+++ b/eval.v
@@ -1,12 +1,11 @@
-module EVAL(input clk, input mclk, input [15:0] Ein, output [15:0] Eout, output [3:0] gcop, output [5:0] ostate, input conn_ea, input conn_et);
+module EVAL(input clk, input clk_enable, input rst, input [15:0] Ein, output [15:0] Eout, output [3:0] gcop, output [5:0] ostate, input conn_ea, input conn_et);
    reg [21:0] rom_output;
-   reg [5:0]  eostate = 6'o0;
+   reg [5:0]  eostate;
    reg [5:0]  enstate;
-   reg [15:0]  Ein_latched;
 
-   always @(posedge clk) begin
-	  Ein_latched <= Ein;
-   end
+`ifdef SIM
+   initial eostate <= 0;
+`endif
 
    wire et_lit = rom_output[21];
    wire ea_lit = rom_output[20];
@@ -23,7 +22,7 @@ module EVAL(input clk, input mclk, input [15:0] Ein, output [15:0] Eout, output
    wire ldN = rom_output[9];
    wire ldX = rom_output[8];
    wire ldV = rom_output[7];
-   wire [3:0] gcop = rom_output[6:3];
+   assign gcop = rom_output[6:3];
    wire [2:0] lit = rom_output[2:0];
 
    wire 	  et_zero = ~|E[15:13];
@@ -94,10 +93,14 @@ module EVAL(input clk, input mclk, input [15:0] Ein, output [15:0] Eout, output
    end // always @ *
 
    always @ (posedge clk) begin
-	  eostate <=
-				et_disp ? (enstate | E[15:13]) :
-				eaz_etz_eqv_disp ? (enstate | {ea_zero, et_zero, 1'b0}) :
-				enstate;
+	  if (rst)
+		eostate = 0;
+	  if (clk_enable) begin
+		 eostate <=
+				   et_disp ? (enstate | E[15:13]) :
+				   eaz_etz_eqv_disp ? (enstate | {ea_zero, et_zero, 1'b0}) :
+				   enstate;
+	  end
    end
 
    assign ostate = eostate;
@@ -127,10 +130,12 @@ module EVAL(input clk, input mclk, input [15:0] Ein, output [15:0] Eout, output
    assign Eout = EfromV | EfromX | EfromXp | EfromN | EfromL | EfromC | EfromLIT;
 
    always @ (posedge clk) begin
-	  if (ldV) V <= E;
-	  if (ldX) X <= E;
-	  if (ldN) N <= E;
-	  if (ldL) L <= E;
-	  if (ldC) C <= E;
+	  if (clk_enable) begin
+		 if (ldV) V <= E;
+		 if (ldX) X <= E;
+		 if (ldN) N <= E;
+		 if (ldL) L <= E;
+		 if (ldC) C <= E;
+	  end
    end
 endmodule // EVAL