X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=gc.v;h=2f94a21edec9c85a3d6f7d1b31c5a365553390d3;hb=9c2d207078b3aae663ad8506f2aae47eda26134b;hp=d4521783c163d4a006c23b9e40ddecaf692cbf68;hpb=44b73af51bca05eb26fd1557a192eed779fc065e;p=clump.git

diff --git a/gc.v b/gc.v
index d452178..2f94a21 100644
--- a/gc.v
+++ b/gc.v
@@ -1,13 +1,16 @@
 `include "gcram.v"
 
-module GC (input clk, input mclk, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do);
+module GC (input clk, input clk_enable, input rst, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do, output [12:0] Pout);
    reg [15:0] rom_output;
-   reg [5:0]  gostate = 6'o0;
+   reg [5:0]  gostate;
    reg [5:0]  gnstate;
-   reg [15:0] Ein_latched = 16'b0100000000000100; // initial value of E
+   reg [15:0] Ein_latched;
 
    always @(posedge clk) begin
-	  Ein_latched <= Ein;
+	  if(rst)
+		Ein_latched <= 16'b0100000000000100; // initial value of E
+	  else if(clk_enable)
+		Ein_latched <= Ein;
    end
 
    wire ga_zero_disp = rom_output[15];
@@ -84,10 +87,13 @@ module GC (input clk, input mclk, input [15:0] Ein, output [15:0] Eout, input [3
    end // always @ *
 
    always @ (posedge clk) begin
-	  gostate <=
-				ga_zero_disp ? (gnstate | ga_zero) :
-				gcop_disp ? (gnstate | gcop) :
-				gnstate;
+	  if(rst)
+		gostate <= 0;
+	  if(clk_enable)
+		gostate <=
+				  ga_zero_disp ? (gnstate | ga_zero) :
+				  gcop_disp ? (gnstate | gcop) :
+				  gnstate;
    end // always @ (posedge clk)
 
    assign ostate = gostate;
@@ -99,6 +105,7 @@ module GC (input clk, input mclk, input [15:0] Ein, output [15:0] Eout, input [3
 
    reg [12:0] A; // latched address
 
+   assign Pout = P;
    assign ram_addr = A;
    assign ram_di = S;
 
@@ -121,10 +128,12 @@ module GC (input clk, input mclk, input [15:0] Ein, output [15:0] Eout, input [3
    assign Eout[15:13] = conn_et ? Gout[15:13] : 0;
 
    always @ (posedge clk) begin
-	  if (ldS) S = G;
-	  if (ldP) P <= G[12:0];
-	  if (ldR) R <= G;
-	  if (ldQ) Q <= G;
-	  if (adr) A <= S[12:0];
+	  if(clk_enable) begin
+		 if (ldS) S = G;
+		 if (ldP) P <= G[12:0];
+		 if (ldR) R <= G;
+		 if (ldQ) Q <= G;
+		 if (adr) A <= S[12:0];
+	  end
    end
 endmodule // GC