X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=gc.v;h=c29cc6d324f73bdbaac49163d975cc3e70c83b62;hb=3f6eb730003a296f425587b10ea084778bf09a6e;hp=2bbada4f0aeac15103c0643e91274aa3feb550d9;hpb=29d6bd4718c5788a15657813c5cad8bb82f12684;p=clump.git

diff --git a/gc.v b/gc.v
index 2bbada4..c29cc6d 100644
--- a/gc.v
+++ b/gc.v
@@ -1,15 +1,16 @@
 `include "gcram.v"
 
-module GC (input clk, input clk_enable, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do);
+module GC (input clk, input clk_enable, input rst, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do);
    reg [15:0] rom_output;
-   reg [5:0]  gostate = 6'o0;
+   reg [5:0]  gostate;
    reg [5:0]  gnstate;
-   reg [15:0] Ein_latched = 16'b0100000000000100; // initial value of E
+   reg [15:0] Ein_latched;
 
    always @(posedge clk) begin
-	  if(clk_enable) begin
+	  if(rst)
+		Ein_latched <= 16'b0100000000000100; // initial value of E
+	  else if(clk_enable)
 		Ein_latched <= Ein;
-	  end
    end
 
    wire ga_zero_disp = rom_output[15];
@@ -86,12 +87,13 @@ module GC (input clk, input clk_enable, input [15:0] Ein, output [15:0] Eout, in
    end // always @ *
 
    always @ (posedge clk) begin
-	  if(clk_enable) begin
-		 gostate <=
-				   ga_zero_disp ? (gnstate | ga_zero) :
-				   gcop_disp ? (gnstate | gcop) :
-				   gnstate;
-	  end
+	  if(rst)
+		gostate <= 0;
+	  if(clk_enable)
+		gostate <=
+				  ga_zero_disp ? (gnstate | ga_zero) :
+				  gcop_disp ? (gnstate | gcop) :
+				  gnstate;
    end // always @ (posedge clk)
 
    assign ostate = gostate;