X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=lisp_processor.v;h=6e27c792a27bb98d430c5b357f30a944c9c31f30;hb=HEAD;hp=a3b1966d8bc7949336560eef04c53a7c639535eb;hpb=08f239778273f85e61256a718d8970e4e1fa4592;p=yule.git

diff --git a/lisp_processor.v b/lisp_processor.v
index a3b1966..6e27c79 100644
--- a/lisp_processor.v
+++ b/lisp_processor.v
@@ -1,3 +1,4 @@
+`include "pll.v"
 `include "gc.v"
 `include "eval.v"
 `include "reader.v"
@@ -25,11 +26,15 @@
 `ifdef SIM
  `define UART_DIVIDE 1
 `else
- `define UART_DIVIDE 625
+ `define UART_DIVIDE 3
 `endif
 
-module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
-   wire [12:0] P;
+module cpu (input CLKin, output [4:0] led, output uart_tx, input uart_rx);
+   wire clk;
+
+   pll pll (.clock_in(CLKin), .clock_out(clk));
+
+   wire [12:0] freeptr;
    wire [15:0] E1;
    wire [15:0] E2;
    wire [3:0] gcop;
@@ -69,13 +74,13 @@ module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
 
    GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do));
 
-   GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .Pout(P));
+   GC gc (.clk(clk), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .freeptr(freeptr));
 
    EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et), .eval_finished(eval_finished));
 
    READER reader (.clk(clk), .clk_enable(reader_clock_enable), .rx_byte(uart_rx_byte), .rx_signal(uart_rx_signal), .finished(reader_finished), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
 
-   WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .tx_byte(uart_tx_byte), .tx_signal(uart_tx_signal), .tx_busy(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .P(P));
+   WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .tx_byte(uart_tx_byte), .tx_signal(uart_tx_signal), .tx_busy(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .freeptr(freeptr));
 
    // UART outputs
    wire       uart_rx_signal;
@@ -88,6 +93,6 @@ module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
    wire 	  uart_tx_signal;
    wire [7:0] uart_tx_byte;
 
-   // 4800 baud uart
+   // 19200 baud uart
    uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
 endmodule