X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=lisp_processor.v;h=6e27c792a27bb98d430c5b357f30a944c9c31f30;hb=HEAD;hp=bb5107f30106d4c6403062d27bfffe2418605145;hpb=eba9336246cb6b2ec09c104a79ef43f8bfc30250;p=clump.git diff --git a/lisp_processor.v b/lisp_processor.v index bb5107f..6e27c79 100644 --- a/lisp_processor.v +++ b/lisp_processor.v @@ -1,8 +1,10 @@ +`include "pll.v" `include "gc.v" `include "eval.v" `include "reader.v" `include "uart.v" `include "writer.v" +`include "controller.v" `define GCOP_NOP 4'd0 `define GCOP_CDR 4'd1 @@ -24,27 +26,15 @@ `ifdef SIM `define UART_DIVIDE 1 `else - `define UART_DIVIDE 625 + `define UART_DIVIDE 3 `endif -module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx); - wire [15:0] result; +module cpu (input CLKin, output [4:0] led, output uart_tx, input uart_rx); + wire clk; - reg [5:0] initial_reset = 30; - always @ (posedge clk) - if (initial_reset) initial_reset <= initial_reset - 1; + pll pll (.clock_in(CLKin), .clock_out(clk)); - wire reset = |initial_reset || reader_active || writer_clock_enable; - reg [1:0] counter = 0; - - wire gc_clock_enable = counter[0] & counter[1] & !reset; - wire eval_clock_enable = counter[0] & !counter[1] & step_eval & !reset; - wire writer_clock_enable = counter[0] & counter[1] & writer_active; - - always @ (posedge clk) - counter <= counter + 1; - - wire [12:0] P; + wire [12:0] freeptr; wire [15:0] E1; wire [15:0] E2; wire [3:0] gcop; @@ -65,26 +55,32 @@ module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx); wire [12:0] writer_ram_addr; - wire reader_active; - - wire ram_we = reader_active ? reader_ram_we : gc_ram_we; - wire [12:0] ram_addr = reader_active ? reader_ram_addr : writer_active ? writer_ram_addr : gc_ram_addr; - wire [15:0] ram_di = reader_active ? reader_ram_di : gc_ram_di; + wire ram_we; + wire [12:0] ram_addr; + wire [15:0] ram_di; wire [15:0] ram_do; + wire eval_finished; + wire reader_finished; wire writer_finished; - reg writer_started = 0; - reg writer_active = 0; + + wire gc_clock_enable; + wire eval_clock_enable; + wire reader_clock_enable; + wire writer_clock_enable; + wire reset; + + CTRL ctrl (.clk(clk), .step_eval(step_eval), .reader_finished(reader_finished), .eval_finished(eval_finished), .writer_finished(writer_finished), .gc_clock_enable(gc_clock_enable), .eval_clock_enable(eval_clock_enable), .reader_clock_enable(reader_clock_enable), .writer_clock_enable(writer_clock_enable), .reset(reset), .gc_ram_we(gc_ram_we), .reader_ram_we(reader_ram_we), .gc_ram_addr(gc_ram_addr), .reader_ram_addr(reader_ram_addr), .writer_ram_addr(writer_ram_addr), .gc_ram_di(gc_ram_di), .reader_ram_di(reader_ram_di), .ram_we(ram_we), .ram_addr(ram_addr), .ram_di(ram_di), .uart_is_receiving(uart_is_receiving), .uart_is_transmitting(uart_is_transmitting), .led(led)); GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do)); - GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .Pout(P)); + GC gc (.clk(clk), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .freeptr(freeptr)); - EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et)); + EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et), .eval_finished(eval_finished)); - READER reader (.clk(clk), .clk_enable(!initial_reset), .uart_rx_byte(uart_rx_byte), .uart_rx_signal(uart_rx_signal), .uart_is_receiving(uart_is_receiving), .active(reader_active), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di)); + READER reader (.clk(clk), .clk_enable(reader_clock_enable), .rx_byte(uart_rx_byte), .rx_signal(uart_rx_signal), .finished(reader_finished), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di)); - WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .uart_tx_byte(uart_tx_byte), .uart_tx_signal(uart_tx_signal), .uart_is_transmitting(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .P(P)); + WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .tx_byte(uart_tx_byte), .tx_signal(uart_tx_signal), .tx_busy(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .freeptr(freeptr)); // UART outputs wire uart_rx_signal; @@ -97,25 +93,6 @@ module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx); wire uart_tx_signal; wire [7:0] uart_tx_byte; - always @ (posedge clk) begin - if(writer_finished) - writer_active <= 0; - - if(reader_active) begin - writer_started <= 0; - end else if(eostate == 5'd7 && !writer_started) begin - writer_started <= 1; - writer_active <= 1; - end - end - - // 4800 baud uart + // 19200 baud uart uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error)); - - // Assign the outputs - assign led[0] = eval_clock_enable; - assign led[1] = uart_is_transmitting; - assign led[2] = uart_is_receiving; - assign led[3] = writer_finished; - assign led[4] = !reset; endmodule