X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=lisp_processor.v;h=910b1735c4ca6ad818aa1499705b50287d2f774c;hb=2155cfe39d5e2b85a06e0df92658e30aade8fc0e;hp=fbcca7e0cdb814d67e1ddbfda503a0741685e64d;hpb=2ed306f8640ffdad28bea2e6487e617e81cdde2c;p=yule.git

diff --git a/lisp_processor.v b/lisp_processor.v
index fbcca7e..910b173 100644
--- a/lisp_processor.v
+++ b/lisp_processor.v
@@ -3,10 +3,12 @@
 `include "gc.v"
 `include "eval.v"
 `include "ram.v"
+`include "reader.v"
 `include "rom.v"
 `include "prescaler.v"
 `include "single_trigger.v"
 `include "uart.v"
+`include "writer.v"
 
 `define GCOP_NOP      4'd0
 `define GCOP_CDR      4'd1
@@ -25,19 +27,32 @@
 `define GCOP_RDQA     4'd14
 `define GCOP_RDQCDRRX 4'd15
 
+`ifdef SIM
+ `define UART_DIVIDE 1
+`else
+ `define UART_DIVIDE 625
+`endif
+
 module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
-   wire [7:0] result;
+   wire [15:0] result;
+
+   reg [5:0]   initial_reset = 30;
+   always @ (posedge clk)
+	 if (initial_reset) initial_reset <= initial_reset - 1;
 
+   wire reset = |initial_reset || reader_active || writer_clock_enable;
    reg [1:0]  counter = 0;
 
-   reg gc_clock = counter[1];
-   wire eval_clock = !counter[1] & step_eval;
+   wire gc_clock_enable   = counter[0] &  counter[1] & !reset;
+   wire eval_clock_enable = counter[0] & !counter[1] & step_eval & !reset;
+   wire writer_clock_enable = counter[0] & counter[1] & writer_active;
 
    always @ (posedge clk)
 	 counter <= counter + 1;
 
-   wire [7:0] E1;
-   wire [7:0] E2;
+   wire [12:0] P;
+   wire [15:0] E1;
+   wire [15:0] E2;
    wire [3:0] gcop;
    wire [5:0] gostate;
    wire [5:0] eostate;
@@ -46,9 +61,36 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
 
    wire 	  step_eval;
 
-   GC gc (.clk(gc_clock), .mclk(clk), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .result(result));
+   wire        gc_ram_we;
+   wire [12:0] gc_ram_addr;
+   wire [15:0] gc_ram_di;
+
+   wire        reader_ram_we;
+   wire [12:0] reader_ram_addr;
+   wire [15:0] reader_ram_di;
+
+   wire [12:0] writer_ram_addr;
+
+   wire 	   reader_active;
+
+   wire        ram_we = reader_active ? reader_ram_we : gc_ram_we;
+   wire [12:0] ram_addr = reader_active ? reader_ram_addr : writer_active ? writer_ram_addr : gc_ram_addr;
+   wire [15:0] ram_di = reader_active ? reader_ram_di : gc_ram_di;
+   wire [15:0] ram_do;
+
+   wire		   writer_finished;
+   reg 		   writer_started = 0;
+   reg 		   writer_active = 0;
 
-   EVAL eval (.clk(eval_clock), .mclk(clk), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
+   GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do));
+
+   GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .Pout(P));
+
+   EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
+
+   READER reader (.clk(clk), .clk_enable(!initial_reset), .uart_rx_byte(uart_rx_byte), .uart_rx_signal(uart_rx_signal), .uart_is_receiving(uart_is_receiving), .active(reader_active), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
+
+   WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .uart_tx_byte(uart_tx_byte), .uart_tx_signal(uart_tx_signal), .uart_is_transmitting(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .P(P));
 
    // UART outputs
    wire       uart_rx_signal;
@@ -57,36 +99,29 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
    wire       uart_is_transmitting;
    wire       uart_rx_error;
 
-   // Input logic
-   wire [3:0] fifo_in;
-   wire [3:0] fifo_out;
-   wire 	  fifo_full;
-   wire 	  fifo_empty;
-   wire 	  fifo_re = 0;//eval_clock & inst == `INST_READ & !fifo_empty;
-   wire 	  fifo_we = uart_rx_signal & !fifo_full;
-
-   ascii_to_hex a2h (.ascii({1'b0, uart_rx_byte[6:0]}), .hex(fifo_in));
-
-   generic_fifo_sc_a #(.dw(4), .aw(4)) fifo
-    (.clk(clk),
-     .rst(1'b1),
-     .re(fifo_re),
-     .we(fifo_we),
-     .din(fifo_in),
-     .dout(fifo_out),
-     .full(fifo_full),
-     .empty(fifo_empty));
-
    // UART logic
-   reg       uart_tx_signal = 1;
-   wire [7:0] uart_tx_byte = result;
+   wire 	  uart_tx_signal;
+   wire [7:0] uart_tx_byte;
+
+   always @ (posedge clk) begin
+	  if(writer_finished)
+		writer_active <= 0;
+
+	  if(reader_active) begin
+		 writer_started <= 0;
+	  end else if(eostate == 5'd7 && !writer_started) begin
+		 writer_started <= 1;
+		 writer_active <= 1;
+	  end
+   end
 
-   // 300 baud uart
-   uart #(.CLOCK_DIVIDE(39)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
+   // 4800 baud uart
+   uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
 
    // Assign the outputs
-   assign led[0] = eval_clock;
+   assign led[0] = eval_clock_enable;
    assign led[1] = uart_is_transmitting;
    assign led[2] = uart_is_receiving;
-   assign led[3] = recv_error;
+   assign led[3] = writer_finished;
+   assign led[4] = !reset;
 endmodule