X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=processor_4.v;h=aa894bf7f60c5ac2f2e8a89dde5c27ce7207ae54;hb=9e30ab0cd6964785b3e01e2f3343e1fe4ee49462;hp=2184846c30af4349c899f6ac4f5da5fe570d31ae;hpb=a051754e2f539c6ed180e93ecf31cdcb95950896;p=yule.git

diff --git a/processor_4.v b/processor_4.v
index 2184846..aa894bf 100644
--- a/processor_4.v
+++ b/processor_4.v
@@ -23,15 +23,6 @@
 `define INST_CAR           4'b1111
 `define INST_CDR           4'b1101
 
-`define STORE_BUTTON       buttons[8]
-`define CLEAR_BUTTON       buttons[9]
-`define PC_INC_BUTTON      buttons[10]
-`define PC_DEC_BUTTON      buttons[11]
-`define PC_CLR_BUTTON      buttons[12]
-`define ACCUM_CLR_BUTTON   buttons[13]
-`define RUN_BUTTON         buttons[14]
-`define EXECUTE_BUTTON     buttons[15]
-
 `define GCOP_NOP      4'd0
 `define GCOP_CDR      4'd1
 `define GCOP_CAR      4'd2
@@ -52,7 +43,7 @@
 // This is a simple four bit accumulator machine. It is a Havard architecture with separate
 // program and user memory address spaces.
 
-module PROCESSOR (input clk, output [23:0] led, output [3:0] indicators, input [15:0] buttons, output uart_tx, input uart_rx);
+module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
    // storage unit
    reg  [7:0] Ein;
    wire [7:0] Eout;
@@ -66,31 +57,14 @@ module PROCESSOR (input clk, output [23:0] led, output [3:0] indicators, input [
 
    reg running = 1;
 
-   always @ (posedge `RUN_BUTTON) begin
-      running <= !running;
-   end
-
-   // Generate running clock
-
-   wire running_counter;
-
-   PRESCALER #(.BITS(1)) scal0 (.clk(clk), .out(running_counter));
-
-   wire running_clk = running & running_counter;
-
-   // Handle execution
-
-   wire execute_trigger;
+   // Generate eval and gc clocks
 
-   SINGLE_TRIGGER trig0 (.clk(clk), .trigger_in(`EXECUTE_BUTTON), .trigger_out(execute_trigger));
-
-   wire running_trigger;
-
-   SINGLE_TRIGGER trig1 (.clk(clk), .trigger_in(running_clk), .trigger_out(running_trigger));
-
-   wire gc_clock = (!running & execute_trigger) | running_clk;
+   reg gc_clock = 0;
    wire eval_clock = !gc_clock & step_eval;
 
+   always @ (posedge clk)
+	  gc_clock <= !gc_clock;
+
    GC gc (.clk(gc_clock), .mclk(clk), .Ein(Ein), .Eout(Eout), .gcop(gcop), .ostate(ostate), .step_eval(step_eval));
 
    // Handle halt
@@ -156,14 +130,6 @@ module PROCESSOR (input clk, output [23:0] led, output [3:0] indicators, input [
    wire [3:0] next = pc + 4'b0001;
    wire [3:0] prev = pc + 4'b1111;
 
-   wire       pc_prev_trigger;
-   wire       pc_next_trigger;
-   wire       pc_zero_trigger;
-
-   SINGLE_TRIGGER trig3 (.clk(clk), .trigger_in(`PC_INC_BUTTON), .trigger_out(pc_next_trigger));
-   SINGLE_TRIGGER trig4 (.clk(clk), .trigger_in(`PC_DEC_BUTTON), .trigger_out(pc_prev_trigger));
-   SINGLE_TRIGGER trig5 (.clk(clk), .trigger_in(`PC_CLR_BUTTON), .trigger_out(pc_zero_trigger));
-
    wire [3:0] newPc =
 			  (inst == `INST_JP) ? argu :
               (inst == `INST_JPZ) & (accum == 4'b0000) ? argu :
@@ -172,9 +138,6 @@ module PROCESSOR (input clk, output [23:0] led, output [3:0] indicators, input [
 			  (inst == `INST_READ) & !fifo_re ? pc :
 			  (inst == `INST_RDQ) & !reading_E ? pc :
               (inst != `INST_HALT) ? next :
-/*              !running & pc_zero_trigger ? 4'b00000 :
-              !running & pc_next_trigger ? next :
-              !running & pc_prev_trigger ? prev : */
               pc;
 
    always @ (posedge eval_clock) begin
@@ -208,8 +171,8 @@ module PROCESSOR (input clk, output [23:0] led, output [3:0] indicators, input [
 
    hex_to_ascii h2a (.hex(accum), .ascii(uart_tx_byte));
 
-   // 300-ish baud uart
-   uart #(.CLOCK_DIVIDE(81)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
+   // 300 baud uart
+   uart #(.CLOCK_DIVIDE(5)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
 
    // GC logic
    always @ (posedge eval_clock) begin
@@ -249,16 +212,18 @@ module PROCESSOR (input clk, output [23:0] led, output [3:0] indicators, input [
    assign led[4] = uart_rx_error;
    assign led[5] = fifo_empty;
    assign led[6] = fifo_full;
-   assign led[7] = fifo_re;*/
+   assign led[7] = fifo_re;
    assign led[7:4] = Ein[3:0];
    assign led[3:0] = Eout[3:0];
 //   assign led[15:8] = programOut;
 //   assign led[15:8] = uart_rx_byte;
-   assign led[15] = step_eval;
-   assign led[14] = eval_clock;
    assign led[13:8] = ostate;
    assign led[19:16] = pc;
    assign led[23:20] = accum;
-   assign indicators = {1'b0, (!running & `EXECUTE_BUTTON) | running_clk, halt, running & !halt};
+   assign indicators = {1'b0, (!running & `EXECUTE_BUTTON) | running_clk, halt, running & !halt};*/
 
+   assign led[0] = eval_clock;
+   assign led[1] = uart_is_transmitting;
+   assign led[2] = uart_is_receiving;
+   assign led[3] = recv_error;
 endmodule