X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=reader.v;h=88e52e71bcf730f7c8a6652304585a64b20271ae;hb=62e5ccb8304550f88f658af70a683936d47c08b2;hp=afe85960f62ff25eed516ef66c49dde4735a7566;hpb=5284821b41df368b5aa571f6ddd2440cfc2a6426;p=clump.git

diff --git a/reader.v b/reader.v
index afe8596..88e52e7 100644
--- a/reader.v
+++ b/reader.v
@@ -3,11 +3,11 @@
 `define STATE_READ1   2'd2
 `define STATE_READ2   2'd3
 
-module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output reg active, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
+module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output reg finished = 0, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
    reg [1:0] state = `STATE_IDLE;
 
-   reg [12:0] words_left = 0;
-   reg [12:0] current_index = 0;
+   reg [12:0] words_left;
+   reg [12:0] current_index;
 
    assign ram_addr = current_index;
 
@@ -21,10 +21,8 @@ module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal
 				words_left[12:8] <= rx_byte[4:0];
 				words_left[7:0] <= 0;
 				current_index <= -1;
-				active <= 1;
 				state <= `STATE_LENGTH;
-			 end else
-			   active <= 0;
+			 end
 		  end
 
 		  `STATE_LENGTH: begin
@@ -47,9 +45,16 @@ module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal
 			 if(rx_signal) begin
 				ram_di[7:0] <= rx_byte;
 				ram_we <= 1;
-				state <= |words_left ? `STATE_READ1 : `STATE_IDLE;
+				if(|words_left) begin
+				   state <= `STATE_READ1;
+				end else begin
+				   state <= `STATE_IDLE;
+				   finished <= 1;
+				end
 			 end
 		  end
 		endcase
-	 end
+	 end // if (clk_enable)
+	 else
+	   finished <= 0;
 endmodule