X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=reader.v;h=88e52e71bcf730f7c8a6652304585a64b20271ae;hb=c6418cc5f2b700f908cc8f330664f38537690a14;hp=8386b532367d7971bc291633f01554afbad29357;hpb=3f6eb730003a296f425587b10ea084778bf09a6e;p=clump.git

diff --git a/reader.v b/reader.v
index 8386b53..88e52e7 100644
--- a/reader.v
+++ b/reader.v
@@ -3,53 +3,58 @@
 `define STATE_READ1   2'd2
 `define STATE_READ2   2'd3
 
-module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart_rx_signal, input uart_is_receiving, output reg active, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
+module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output reg finished = 0, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
    reg [1:0] state = `STATE_IDLE;
 
-   reg [12:0] bytes_left = 0;
-   reg [12:0] current_index = 0;
+   reg [12:0] words_left;
+   reg [12:0] current_index;
 
    assign ram_addr = current_index;
 
    always @ (posedge clk)
 	 if (clk_enable) begin
-		if(!uart_rx_signal) ram_we <= 0;
+		if(!rx_signal) ram_we <= 0;
 
 		case(state)
 		  `STATE_IDLE: begin
-			 if(uart_rx_signal) begin
-				bytes_left[12:8] <= uart_rx_byte[4:0];
-				bytes_left[7:0] <= 0;
+			 if(rx_signal) begin
+				words_left[12:8] <= rx_byte[4:0];
+				words_left[7:0] <= 0;
 				current_index <= -1;
-				active <= 1;
 				state <= `STATE_LENGTH;
-			 end else
-			   active <= 0;
+			 end
 		  end
 
 		  `STATE_LENGTH: begin
-			 if(uart_rx_signal) begin
-				bytes_left[7:0] <= uart_rx_byte;
+			 if(rx_signal) begin
+				words_left[7:0] <= rx_byte;
 				state <= `STATE_READ1;
 			 end
 		  end
 
 		  `STATE_READ1: begin
-			 if(uart_rx_signal) begin
-				ram_di[15:8] <= uart_rx_byte;
+			 if(rx_signal) begin
+				ram_di[15:8] <= rx_byte;
 				current_index <= current_index + 1;
-				bytes_left <= bytes_left - 1;
+				words_left <= words_left - 1;
 				state <= `STATE_READ2;
 			 end
 		  end
 
 		  `STATE_READ2: begin
-			 if(uart_rx_signal) begin
-				ram_di[7:0] <= uart_rx_byte;
+			 if(rx_signal) begin
+				ram_di[7:0] <= rx_byte;
 				ram_we <= 1;
-				state <= |bytes_left ? `STATE_READ1 : `STATE_IDLE;
+				if(|words_left) begin
+				   state <= `STATE_READ1;
+				end else begin
+				   state <= `STATE_IDLE;
+				   finished <= 1;
+				end
 			 end
 		  end
 		endcase
-	 end
+	 end // if (clk_enable)
+	 else
+	   finished <= 0;
 endmodule