X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=writer.v;h=1db21f1f45141bc5c924d72f1383a9d1674b0800;hb=5284821b41df368b5aa571f6ddd2440cfc2a6426;hp=c68a8af35ed7e9f930b4739ef354c1a454535b1e;hpb=eba9336246cb6b2ec09c104a79ef43f8bfc30250;p=clump.git

diff --git a/writer.v b/writer.v
index c68a8af..1db21f1 100644
--- a/writer.v
+++ b/writer.v
@@ -3,7 +3,7 @@
 `define STATE_WRITE2       2'b10
 `define STATE_INCREMENT    2'b11
 
-module WRITER (input clk, input clk_enable, output reg [7:0] uart_tx_byte, output reg uart_tx_signal = 0, input uart_is_transmitting, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] P);
+module WRITER (input clk, input clk_enable, output reg [7:0] tx_byte, output reg tx_signal = 0, input tx_busy, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] P);
    reg [1:0] state = `STATE_START;
 
    reg [12:0] current_index;
@@ -13,8 +13,8 @@ module WRITER (input clk, input clk_enable, output reg [7:0] uart_tx_byte, outpu
 
    always @ (posedge clk) begin
 	 if (clk_enable) begin
-		if(uart_tx_signal)
-		  uart_tx_signal <= 0;
+		if(tx_signal)
+		  tx_signal <= 0;
 
 		case(state)
 		  `STATE_START: begin
@@ -25,17 +25,17 @@ module WRITER (input clk, input clk_enable, output reg [7:0] uart_tx_byte, outpu
 		  end
 
 		  `STATE_WRITE1: begin
-			 if(!uart_is_transmitting && !uart_tx_signal) begin
-				uart_tx_signal <= 1;
-				uart_tx_byte <= ram_do[15:8];
+			 if(!tx_busy && !tx_signal) begin
+				tx_signal <= 1;
+				tx_byte <= ram_do[15:8];
 				state <= `STATE_WRITE2;
 			 end
 		  end
 
 		  `STATE_WRITE2: begin
-			 if(!uart_is_transmitting && !uart_tx_signal) begin
-				uart_tx_signal <= 1;
-				uart_tx_byte <= ram_do[7:0];
+			 if(!tx_busy && !tx_signal) begin
+				tx_signal <= 1;
+				tx_byte <= ram_do[7:0];
 				state <= `STATE_INCREMENT;
 			 end
 		  end