X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=writer.v;h=1db21f1f45141bc5c924d72f1383a9d1674b0800;hb=c6418cc5f2b700f908cc8f330664f38537690a14;hp=37f6e0a3fba1da519db22d74cf78830c69aa9eac;hpb=eb54e6d0b78c3d1c4edcc2f213f971e2e1922bac;p=yule.git

diff --git a/writer.v b/writer.v
index 37f6e0a..1db21f1 100644
--- a/writer.v
+++ b/writer.v
@@ -3,7 +3,7 @@
 `define STATE_WRITE2       2'b10
 `define STATE_INCREMENT    2'b11
 
-module WRITER (input clk, input clk_enable, output reg [7:0] uart_tx_byte, output reg uart_tx_signal = 0, input uart_is_transmitting, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] P);
+module WRITER (input clk, input clk_enable, output reg [7:0] tx_byte, output reg tx_signal = 0, input tx_busy, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] P);
    reg [1:0] state = `STATE_START;
 
    reg [12:0] current_index;
@@ -11,10 +11,10 @@ module WRITER (input clk, input clk_enable, output reg [7:0] uart_tx_byte, outpu
 
    assign ram_addr = current_index;
 
-   always @ (posedge clk)
+   always @ (posedge clk) begin
 	 if (clk_enable) begin
-		if(uart_tx_signal)
-		  uart_tx_signal <= 0;
+		if(tx_signal)
+		  tx_signal <= 0;
 
 		case(state)
 		  `STATE_START: begin
@@ -25,17 +25,17 @@ module WRITER (input clk, input clk_enable, output reg [7:0] uart_tx_byte, outpu
 		  end
 
 		  `STATE_WRITE1: begin
-			 if(!uart_is_transmitting && !uart_tx_signal) begin
-				uart_tx_signal <= 1;
-				uart_tx_byte <= ram_do[15:8];
+			 if(!tx_busy && !tx_signal) begin
+				tx_signal <= 1;
+				tx_byte <= ram_do[15:8];
 				state <= `STATE_WRITE2;
 			 end
 		  end
 
 		  `STATE_WRITE2: begin
-			 if(!uart_is_transmitting && !uart_tx_signal) begin
-				uart_tx_signal <= 1;
-				uart_tx_byte <= ram_do[7:0];
+			 if(!tx_busy && !tx_signal) begin
+				tx_signal <= 1;
+				tx_byte <= ram_do[7:0];
 				state <= `STATE_INCREMENT;
 			 end
 		  end
@@ -50,5 +50,8 @@ module WRITER (input clk, input clk_enable, output reg [7:0] uart_tx_byte, outpu
 			 end
 		  end
 		endcase // case (state)
-	 end
+	 end // if (clk_enable)
+	 else
+	   finished <= 0;
+   end
 endmodule