X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=writer.v;h=37f6e0a3fba1da519db22d74cf78830c69aa9eac;hb=eb54e6d0b78c3d1c4edcc2f213f971e2e1922bac;hp=7ef47ffa6688fb9923cea00f31ccc815d656ff92;hpb=3f6eb730003a296f425587b10ea084778bf09a6e;p=clump.git

diff --git a/writer.v b/writer.v
index 7ef47ff..37f6e0a 100644
--- a/writer.v
+++ b/writer.v
@@ -1,14 +1,15 @@
-`define STATE_WRITE_TYPE 3'd0
-`define STATE_WRITE1     3'd1
-`define STATE_WRITE2     3'd2
-`define STATE_WRITE3     3'd3
-`define STATE_WRITE4     3'd4
+`define STATE_START        2'b00
+`define STATE_WRITE1       2'b01
+`define STATE_WRITE2       2'b10
+`define STATE_INCREMENT    2'b11
 
-module WRITER (input clk, input clk_enable, output [7:0] uart_tx_byte, output reg uart_tx_signal = 0, input uart_is_transmitting, output reg finished = 0, input [15:0] result);
-   reg [2:0] state = `STATE_WRITE_TYPE;
-   reg [3:0] tx_hex = 0;
+module WRITER (input clk, input clk_enable, output reg [7:0] uart_tx_byte, output reg uart_tx_signal = 0, input uart_is_transmitting, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] P);
+   reg [1:0] state = `STATE_START;
 
-   hex_to_ascii h2a (.hex(tx_hex), .ascii(uart_tx_byte));
+   reg [12:0] current_index;
+   reg [12:0] freeptr;
+
+   assign ram_addr = current_index;
 
    always @ (posedge clk)
 	 if (clk_enable) begin
@@ -16,19 +17,17 @@ module WRITER (input clk, input clk_enable, output [7:0] uart_tx_byte, output re
 		  uart_tx_signal <= 0;
 
 		case(state)
-		  `STATE_WRITE_TYPE: begin
+		  `STATE_START: begin
 			 finished <= 0;
-			 if(!uart_is_transmitting && !uart_tx_signal) begin
-				uart_tx_signal <= 1;
-				tx_hex <= {1'b0, result[15:13]};
-				state <= `STATE_WRITE1;
-			 end
+			 current_index <= 4;
+			 freeptr <= P;
+			 state <= `STATE_WRITE1;
 		  end
 
 		  `STATE_WRITE1: begin
 			 if(!uart_is_transmitting && !uart_tx_signal) begin
 				uart_tx_signal <= 1;
-				tx_hex <= {3'b0, result[12]};
+				uart_tx_byte <= ram_do[15:8];
 				state <= `STATE_WRITE2;
 			 end
 		  end
@@ -36,27 +35,20 @@ module WRITER (input clk, input clk_enable, output [7:0] uart_tx_byte, output re
 		  `STATE_WRITE2: begin
 			 if(!uart_is_transmitting && !uart_tx_signal) begin
 				uart_tx_signal <= 1;
-				tx_hex <= result[11:8];
-				state <= `STATE_WRITE3;
+				uart_tx_byte <= ram_do[7:0];
+				state <= `STATE_INCREMENT;
 			 end
 		  end
 
-		  `STATE_WRITE3: begin
-			 if(!uart_is_transmitting && !uart_tx_signal) begin
-				uart_tx_signal <= 1;
-				tx_hex <= result[7:4];
-				state <= `STATE_WRITE4;
-			 end
-		  end
-
-		  `STATE_WRITE4: begin
-			 if(!uart_is_transmitting && !uart_tx_signal) begin
-				uart_tx_signal <= 1;
-				tx_hex <= result[3:0];
+		  `STATE_INCREMENT: begin
+			 current_index <= current_index + 1;
+			 if(current_index >= freeptr) begin
 				finished <= 1;
-				state <= `STATE_WRITE_TYPE;
+				state <= `STATE_START;
+			 end else begin
+				state <= `STATE_WRITE1;
 			 end
 		  end
-		endcase
+		endcase // case (state)
 	 end
 endmodule