X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=writer.v;h=8ac04ac51a50f591fbd2ad0e5ed917ce9f9338aa;hb=HEAD;hp=7ef47ffa6688fb9923cea00f31ccc815d656ff92;hpb=3f6eb730003a296f425587b10ea084778bf09a6e;p=yule.git

diff --git a/writer.v b/writer.v
index 7ef47ff..8ac04ac 100644
--- a/writer.v
+++ b/writer.v
@@ -1,62 +1,70 @@
-`define STATE_WRITE_TYPE 3'd0
-`define STATE_WRITE1     3'd1
-`define STATE_WRITE2     3'd2
-`define STATE_WRITE3     3'd3
-`define STATE_WRITE4     3'd4
+`define STATE_START        3'b000
+`define STATE_WRITE1_WAIT  3'b001
+`define STATE_WRITE1       3'b010
+`define STATE_WRITE2_WAIT  3'b011
+`define STATE_WRITE2       3'b100
+`define STATE_INCREMENT    3'b101
+`define STATE_FINISHED     3'b111
 
-module WRITER (input clk, input clk_enable, output [7:0] uart_tx_byte, output reg uart_tx_signal = 0, input uart_is_transmitting, output reg finished = 0, input [15:0] result);
-   reg [2:0] state = `STATE_WRITE_TYPE;
-   reg [3:0] tx_hex = 0;
+module WRITER (input clk, input clk_enable, output [7:0] tx_byte, output tx_signal, input tx_busy, output finished, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] freeptr);
+   reg [2:0] state = `STATE_START;
+   reg [12:0] current_index;
 
-   hex_to_ascii h2a (.hex(tx_hex), .ascii(uart_tx_byte));
+   assign ram_addr = current_index;
+   assign finished = state == `STATE_FINISHED;
 
-   always @ (posedge clk)
-	 if (clk_enable) begin
-		if(uart_tx_signal)
-		  uart_tx_signal <= 0;
+   always @* begin
+	  case(state)
+		`STATE_WRITE1: begin
+		   tx_signal <= 1;
+		   tx_byte   <= ram_do[15:8];
+		end
+
+		`STATE_WRITE2: begin
+		   tx_signal <= 1;
+		   tx_byte   <= ram_do[7:0];
+		end
+
+		default: begin
+		   tx_signal <= 0;
+		   tx_byte   <= 12'dx;
+		end
+	  endcase
+   end
 
+   always @ (posedge clk) begin
+	 if (clk_enable) begin
 		case(state)
-		  `STATE_WRITE_TYPE: begin
-			 finished <= 0;
-			 if(!uart_is_transmitting && !uart_tx_signal) begin
-				uart_tx_signal <= 1;
-				tx_hex <= {1'b0, result[15:13]};
-				state <= `STATE_WRITE1;
-			 end
+		  `STATE_START: begin
+			 current_index <= 4;
+			 state <= `STATE_WRITE1_WAIT;
 		  end
 
-		  `STATE_WRITE1: begin
-			 if(!uart_is_transmitting && !uart_tx_signal) begin
-				uart_tx_signal <= 1;
-				tx_hex <= {3'b0, result[12]};
-				state <= `STATE_WRITE2;
-			 end
+		  `STATE_WRITE1_WAIT: begin
+			 if(!tx_busy) state <= `STATE_WRITE1;
 		  end
 
-		  `STATE_WRITE2: begin
-			 if(!uart_is_transmitting && !uart_tx_signal) begin
-				uart_tx_signal <= 1;
-				tx_hex <= result[11:8];
-				state <= `STATE_WRITE3;
-			 end
-		  end
+		  `STATE_WRITE1: state <= `STATE_WRITE2_WAIT;
 
-		  `STATE_WRITE3: begin
-			 if(!uart_is_transmitting && !uart_tx_signal) begin
-				uart_tx_signal <= 1;
-				tx_hex <= result[7:4];
-				state <= `STATE_WRITE4;
-			 end
+		  `STATE_WRITE2_WAIT: begin
+			 if(!tx_busy) state <= `STATE_WRITE2;
 		  end
 
-		  `STATE_WRITE4: begin
-			 if(!uart_is_transmitting && !uart_tx_signal) begin
-				uart_tx_signal <= 1;
-				tx_hex <= result[3:0];
-				finished <= 1;
-				state <= `STATE_WRITE_TYPE;
+		  `STATE_WRITE2: state <= `STATE_INCREMENT;
+
+		  `STATE_INCREMENT: begin
+			 current_index <= current_index + 1;
+			 if(current_index >= freeptr) begin
+				state <= `STATE_FINISHED;
+			 end else begin
+				state <= `STATE_WRITE1_WAIT;
 			 end
 		  end
-		endcase
-	 end
+
+		  `STATE_FINISHED: state <= `STATE_START;
+
+		  default: state <= `STATE_START;
+		endcase // case (state)
+	 end // if (clk_enable)
+   end
 endmodule