X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=yosys-sim-script;h=10f21eca9ecd507c127ebf4655dc12afc7beca53;hb=HEAD;hp=9cffede952a7db8d46e6e4a9b1e7a326590ea9ec;hpb=ab3ea03d7c7575d8d9917122a463935867a8572c;p=yule.git

diff --git a/yosys-sim-script b/yosys-sim-script
index 9cffede..10f21ec 100755
--- a/yosys-sim-script
+++ b/yosys-sim-script
@@ -1,3 +1,3 @@
-read_verilog -sv -DSIM flash.v
-prep -top top -nordff
-sim -clock CLK -vcd test.vcd -n 3000
+read_verilog -sv -DSIM lisp_processor.v
+prep -top cpu -nordff
+sim -clock clk -vcd test.vcd -n 3000