X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=yosys-sim-script;h=10f21eca9ecd507c127ebf4655dc12afc7beca53;hb=e7b86bf0143c9bef1c26248fcda4fb2f2558b519;hp=eae3049a4d11e22db9243864abcea405992f8dee;hpb=a051754e2f539c6ed180e93ecf31cdcb95950896;p=yule.git

diff --git a/yosys-sim-script b/yosys-sim-script
index eae3049..10f21ec 100755
--- a/yosys-sim-script
+++ b/yosys-sim-script
@@ -1,3 +1,3 @@
-read_verilog -sv flash.v
-prep -top top -nordff
-sim -clock CLK -vcd test.vcd -n 200
+read_verilog -sv -DSIM lisp_processor.v
+prep -top cpu -nordff
+sim -clock clk -vcd test.vcd -n 3000