X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=yosys-sim-script;h=9cffede952a7db8d46e6e4a9b1e7a326590ea9ec;hb=29d6bd4718c5788a15657813c5cad8bb82f12684;hp=eae3049a4d11e22db9243864abcea405992f8dee;hpb=a051754e2f539c6ed180e93ecf31cdcb95950896;p=yule.git

diff --git a/yosys-sim-script b/yosys-sim-script
index eae3049..9cffede 100755
--- a/yosys-sim-script
+++ b/yosys-sim-script
@@ -1,3 +1,3 @@
-read_verilog -sv flash.v
+read_verilog -sv -DSIM flash.v
 prep -top top -nordff
-sim -clock CLK -vcd test.vcd -n 200
+sim -clock CLK -vcd test.vcd -n 3000