X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=yosys-sim-script;h=9cffede952a7db8d46e6e4a9b1e7a326590ea9ec;hb=ab3ea03d7c7575d8d9917122a463935867a8572c;hp=965efd1672ab2382a21d9c02d073ea487a6adeb7;hpb=b5efed3aa26a11e1da3639806afea5c772fff7aa;p=yule.git

diff --git a/yosys-sim-script b/yosys-sim-script
index 965efd1..9cffede 100755
--- a/yosys-sim-script
+++ b/yosys-sim-script
@@ -1,3 +1,3 @@
-read_verilog -sv flash.v
+read_verilog -sv -DSIM flash.v
 prep -top top -nordff
-sim -clock CLK -vcd test.vcd -n 1000
+sim -clock CLK -vcd test.vcd -n 3000