X-Git-Url: http://git.ieval.ro/?a=blobdiff_plain;f=yosys-sim-script;h=f82bfb456f6efde9e1f09e2f3d34d45b4e070ef6;hb=46a95fd39e0ef114dd837bed285f8ca6acf6bb32;hp=10f21eca9ecd507c127ebf4655dc12afc7beca53;hpb=62e5ccb8304550f88f658af70a683936d47c08b2;p=clump.git

diff --git a/yosys-sim-script b/yosys-sim-script
index 10f21ec..f82bfb4 100755
--- a/yosys-sim-script
+++ b/yosys-sim-script
@@ -1,3 +1,3 @@
-read_verilog -sv -DSIM lisp_processor.v
+read_verilog -sv -DSIM toplevel.v
 prep -top cpu -nordff
 sim -clock clk -vcd test.vcd -n 3000