Some renamings

diff --git a/lisp_processor.v b/lisp_processor.v
index bb5107f30106d4c6403062d27bfffe2418605145..c4f737219d4a2fd5cc8f89095e78069161418b91 100644 (file)
--- a/lisp_processor.v
+++ b/lisp_processor.v
@@ -82,9 +82,9 @@ module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
 
    EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
 
-   READER reader (.clk(clk), .clk_enable(!initial_reset), .uart_rx_byte(uart_rx_byte), .uart_rx_signal(uart_rx_signal), .uart_is_receiving(uart_is_receiving), .active(reader_active), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
+   READER reader (.clk(clk), .clk_enable(!initial_reset), .rx_byte(uart_rx_byte), .rx_signal(uart_rx_signal), .active(reader_active), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
 
-   WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .uart_tx_byte(uart_tx_byte), .uart_tx_signal(uart_tx_signal), .uart_is_transmitting(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .P(P));
+   WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .tx_byte(uart_tx_byte), .tx_signal(uart_tx_signal), .tx_busy(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .P(P));
 
    // UART outputs
    wire       uart_rx_signal;

diff --git a/reader.v b/reader.v
index 2f06a8466b15bb4d4f8a5d00bcda2b382bf75c40..afe85960f62ff25eed516ef66c49dde4735a7566 100644 (file)
--- a/reader.v
+++ b/reader.v
@@ -3,7 +3,7 @@
 `define STATE_READ1   2'd2
 `define STATE_READ2   2'd3
 
-module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart_rx_signal, input uart_is_receiving, output reg active, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
+module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output reg active, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
    reg [1:0] state = `STATE_IDLE;
 
    reg [12:0] words_left = 0;
@@ -13,12 +13,12 @@ module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart
 
    always @ (posedge clk)
         if (clk_enable) begin
-               if(!uart_rx_signal) ram_we <= 0;
+               if(!rx_signal) ram_we <= 0;
 
                case(state)
                  `STATE_IDLE: begin
-                        if(uart_rx_signal) begin
-                               words_left[12:8] <= uart_rx_byte[4:0];
+                        if(rx_signal) begin
+                               words_left[12:8] <= rx_byte[4:0];
                                words_left[7:0] <= 0;
                                current_index <= -1;
                                active <= 1;
@@ -28,15 +28,15 @@ module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart
                  end
 
                  `STATE_LENGTH: begin
-                        if(uart_rx_signal) begin
-                               words_left[7:0] <= uart_rx_byte;
+                        if(rx_signal) begin
+                               words_left[7:0] <= rx_byte;
                                state <= `STATE_READ1;
                         end
                  end
 
                  `STATE_READ1: begin
-                        if(uart_rx_signal) begin
-                               ram_di[15:8] <= uart_rx_byte;
+                        if(rx_signal) begin
+                               ram_di[15:8] <= rx_byte;
                                current_index <= current_index + 1;
                                words_left <= words_left - 1;
                                state <= `STATE_READ2;
@@ -44,8 +44,8 @@ module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart
                  end
 
                  `STATE_READ2: begin
-                        if(uart_rx_signal) begin
-                               ram_di[7:0] <= uart_rx_byte;
+                        if(rx_signal) begin
+                               ram_di[7:0] <= rx_byte;
                                ram_we <= 1;
                                state <= |words_left ? `STATE_READ1 : `STATE_IDLE;
                         end

diff --git a/writer.v b/writer.v
index c68a8af35ed7e9f930b4739ef354c1a454535b1e..1db21f1f45141bc5c924d72f1383a9d1674b0800 100644 (file)
--- a/writer.v
+++ b/writer.v
@@ -3,7 +3,7 @@
 `define STATE_WRITE2       2'b10
 `define STATE_INCREMENT    2'b11
 
-module WRITER (input clk, input clk_enable, output reg [7:0] uart_tx_byte, output reg uart_tx_signal = 0, input uart_is_transmitting, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] P);
+module WRITER (input clk, input clk_enable, output reg [7:0] tx_byte, output reg tx_signal = 0, input tx_busy, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] P);
    reg [1:0] state = `STATE_START;
 
    reg [12:0] current_index;
@@ -13,8 +13,8 @@ module WRITER (input clk, input clk_enable, output reg [7:0] uart_tx_byte, outpu
 
    always @ (posedge clk) begin
         if (clk_enable) begin
-               if(uart_tx_signal)
-                 uart_tx_signal <= 0;
+               if(tx_signal)
+                 tx_signal <= 0;
 
                case(state)
                  `STATE_START: begin
@@ -25,17 +25,17 @@ module WRITER (input clk, input clk_enable, output reg [7:0] uart_tx_byte, outpu
                  end
 
                  `STATE_WRITE1: begin
-                        if(!uart_is_transmitting && !uart_tx_signal) begin
-                               uart_tx_signal <= 1;
-                               uart_tx_byte <= ram_do[15:8];
+                        if(!tx_busy && !tx_signal) begin
+                               tx_signal <= 1;
+                               tx_byte <= ram_do[15:8];
                                state <= `STATE_WRITE2;
                         end
                  end
 
                  `STATE_WRITE2: begin
-                        if(!uart_is_transmitting && !uart_tx_signal) begin
-                               uart_tx_signal <= 1;
-                               uart_tx_byte <= ram_do[7:0];
+                        if(!tx_busy && !tx_signal) begin
+                               tx_signal <= 1;
+                               tx_byte <= ram_do[7:0];
                                state <= `STATE_INCREMENT;
                         end
                  end