GC needs no reset

diff --git a/gc.v b/gc.v
index d05de6317a69beb00abb71bdd7cf74af47a89c91..d0da0c1b3beb3c7b31327a9009566c4a4e9bf50e 100644 (file)
--- a/gc.v
+++ b/gc.v
@@ -1,6 +1,6 @@
 `include "gcram.v"
 
-module GC (input clk, input clk_enable, input rst, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do, output [12:0] freeptr);
+module GC (input clk, input clk_enable, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do, output [12:0] freeptr);
    reg [15:0] rom_output;
    reg [5:0]  gostate;
    reg [5:0]  gnstate;
@@ -85,13 +85,13 @@ module GC (input clk, input clk_enable, input rst, input [15:0] Ein, output [15:
    end // always @ *
 
    always @ (posedge clk) begin
-         if(rst)
-               gostate <= 0;
          if(clk_enable)
                gostate <=
                                  ga_zero_disp ? (gnstate | ga_zero) :
                                  gcop_disp ? (gnstate | gcop) :
                                  gnstate;
+         else
+               gostate <= 0;
    end // always @ (posedge clk)
 
    assign ostate = gostate;

diff --git a/lisp_processor.v b/lisp_processor.v
index fbc44673d5f9961a5cb7b20e37ba3bfcc1b79cba..fc84e427ad149084531d8846dd633084a113aa70 100644 (file)
--- a/lisp_processor.v
+++ b/lisp_processor.v
@@ -74,7 +74,7 @@ module cpu (input CLKin, output [4:0] led, output uart_tx, input uart_rx);
 
    GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do));
 
-   GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .freeptr(freeptr));
+   GC gc (.clk(clk), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .freeptr(freeptr));
 
    EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et), .eval_finished(eval_finished));