From: Marius Gavrilescu <marius@ieval.ro>
Date: Mon, 19 Mar 2018 15:24:38 +0000 (+0200)
Subject: Write reader.v in more combinational style
X-Git-Url: http://git.ieval.ro/?a=commitdiff_plain;h=2fb3df000de59bec2436a88db662c9ab94d69f33;p=clump.git

Write reader.v in more combinational style
---

diff --git a/reader.v b/reader.v
index e96131e..50cee43 100644
--- a/reader.v
+++ b/reader.v
@@ -1,20 +1,22 @@
-`define STATE_IDLE    2'd0
-`define STATE_LENGTH  2'd1
-`define STATE_READ1   2'd2
-`define STATE_READ2   2'd3
+`define STATE_IDLE     3'd0
+`define STATE_LENGTH   3'd1
+`define STATE_READ1    3'd2
+`define STATE_READ2    3'd3
+`define STATE_WRITE    3'd4
+`define STATE_FINISHED 3'd5
 
-module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output reg finished = 0, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
-   reg [1:0] state = `STATE_IDLE;
+module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output finished, output ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
+   reg [2:0] state = `STATE_IDLE;
 
    reg [12:0] total_words;
    reg [12:0] current_index;
 
    assign ram_addr = current_index;
+   assign finished = state == `STATE_FINISHED;
+   assign ram_we   = state == `STATE_WRITE;
 
    always @ (posedge clk)
 	 if (clk_enable) begin
-		if(!rx_signal) ram_we <= 0;
-
 		case(state)
 		  `STATE_IDLE: begin
 			 if(rx_signal) begin
@@ -42,17 +44,20 @@ module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal
 		  `STATE_READ2: begin
 			 if(rx_signal) begin
 				ram_di[7:0] <= rx_byte;
-				ram_we <= 1;
-				if(current_index == total_words) begin
-				   state <= `STATE_READ1;
-				end else begin
-				   state <= `STATE_IDLE;
-				   finished <= 1;
-				end
+				state <= `STATE_WRITE;
+			 end
+		  end
+
+		  `STATE_WRITE: begin
+			 if(current_index + 1 == total_words) begin
+				state <= `STATE_FINISHED;
+			 end else begin
+				state <= `STATE_READ1;
 			 end
 		  end
+
+		  `STATE_FINISHED: state <= `STATE_IDLE;
+		  default:         state <= `STATE_IDLE;
 		endcase
 	 end // if (clk_enable)
-	 else
-	   finished <= 0;
 endmodule