From: Marius Gavrilescu <marius@ieval.ro>
Date: Tue, 20 Feb 2018 02:38:50 +0000 (+0000)
Subject: Reset pins + add reader and writer
X-Git-Url: http://git.ieval.ro/?a=commitdiff_plain;h=3f6eb730003a296f425587b10ea084778bf09a6e;p=yule.git

Reset pins + add reader and writer
---

diff --git a/eval.v b/eval.v
index 75a979c..355a9ff 100644
--- a/eval.v
+++ b/eval.v
@@ -1,6 +1,6 @@
-module EVAL(input clk, input clk_enable, input [15:0] Ein, output [15:0] Eout, output [3:0] gcop, output [5:0] ostate, input conn_ea, input conn_et);
+module EVAL(input clk, input clk_enable, input rst, input [15:0] Ein, output [15:0] Eout, output [3:0] gcop, output [5:0] ostate, input conn_ea, input conn_et);
    reg [21:0] rom_output;
-   reg [5:0]  eostate = 6'o0;
+   reg [5:0]  eostate;
    reg [5:0]  enstate;
    reg [15:0]  Ein_latched;
 
@@ -25,7 +25,7 @@ module EVAL(input clk, input clk_enable, input [15:0] Ein, output [15:0] Eout, o
    wire ldN = rom_output[9];
    wire ldX = rom_output[8];
    wire ldV = rom_output[7];
-   wire [3:0] gcop = rom_output[6:3];
+   assign gcop = rom_output[6:3];
    wire [2:0] lit = rom_output[2:0];
 
    wire 	  et_zero = ~|E[15:13];
@@ -96,6 +96,8 @@ module EVAL(input clk, input clk_enable, input [15:0] Ein, output [15:0] Eout, o
    end // always @ *
 
    always @ (posedge clk) begin
+	  if (rst)
+		eostate = 0;
 	  if (clk_enable) begin
 		 eostate <=
 				   et_disp ? (enstate | E[15:13]) :
diff --git a/gc.v b/gc.v
index 2bbada4..c29cc6d 100644
--- a/gc.v
+++ b/gc.v
@@ -1,15 +1,16 @@
 `include "gcram.v"
 
-module GC (input clk, input clk_enable, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do);
+module GC (input clk, input clk_enable, input rst, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do);
    reg [15:0] rom_output;
-   reg [5:0]  gostate = 6'o0;
+   reg [5:0]  gostate;
    reg [5:0]  gnstate;
-   reg [15:0] Ein_latched = 16'b0100000000000100; // initial value of E
+   reg [15:0] Ein_latched;
 
    always @(posedge clk) begin
-	  if(clk_enable) begin
+	  if(rst)
+		Ein_latched <= 16'b0100000000000100; // initial value of E
+	  else if(clk_enable)
 		Ein_latched <= Ein;
-	  end
    end
 
    wire ga_zero_disp = rom_output[15];
@@ -86,12 +87,13 @@ module GC (input clk, input clk_enable, input [15:0] Ein, output [15:0] Eout, in
    end // always @ *
 
    always @ (posedge clk) begin
-	  if(clk_enable) begin
-		 gostate <=
-				   ga_zero_disp ? (gnstate | ga_zero) :
-				   gcop_disp ? (gnstate | gcop) :
-				   gnstate;
-	  end
+	  if(rst)
+		gostate <= 0;
+	  if(clk_enable)
+		gostate <=
+				  ga_zero_disp ? (gnstate | ga_zero) :
+				  gcop_disp ? (gnstate | gcop) :
+				  gnstate;
    end // always @ (posedge clk)
 
    assign ostate = gostate;
diff --git a/lisp_processor.v b/lisp_processor.v
index 2ae446f..fc71e74 100644
--- a/lisp_processor.v
+++ b/lisp_processor.v
@@ -3,10 +3,12 @@
 `include "gc.v"
 `include "eval.v"
 `include "ram.v"
+`include "reader.v"
 `include "rom.v"
 `include "prescaler.v"
 `include "single_trigger.v"
 `include "uart.v"
+`include "writer.v"
 
 `define GCOP_NOP      4'd0
 `define GCOP_CDR      4'd1
@@ -25,6 +27,12 @@
 `define GCOP_RDQA     4'd14
 `define GCOP_RDQCDRRX 4'd15
 
+`ifdef SIM
+ `define UART_DIVIDE 1
+`else
+ `define UART_DIVIDE 39
+`endif
+
 module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
    wire [15:0] result;
 
@@ -32,10 +40,11 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
    always @ (posedge clk)
 	 if (initial_reset) initial_reset <= initial_reset - 1;
 
+   wire reset = |initial_reset || reader_active || writer_clock_enable;
    reg [1:0]  counter = 0;
 
-   wire gc_clock_enable   = counter[0] &  counter[1] & !initial_reset;
-   wire eval_clock_enable = counter[0] & !counter[1] & step_eval & !initial_reset;
+   wire gc_clock_enable   = counter[0] &  counter[1] & !reset;
+   wire eval_clock_enable = counter[0] & !counter[1] & step_eval & !reset;
 
    always @ (posedge clk)
 	 counter <= counter + 1;
@@ -50,16 +59,37 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
 
    wire 	  step_eval;
 
-   wire        ram_we;
-   wire [12:0] ram_addr;
-   wire [15:0] ram_di;
+   wire        gc_ram_we;
+   wire [12:0] gc_ram_addr;
+   wire [15:0] gc_ram_di;
+
+   wire        reader_ram_we;
+   wire [12:0] reader_ram_addr;
+   wire [15:0] reader_ram_di;
+
+   wire [12:0] writer_ram_addr;
+
+   wire 	   reader_active;
+
+   wire        ram_we = reader_active ? reader_ram_we : gc_ram_we;
+   wire [12:0] ram_addr = reader_active ? reader_ram_addr : writer_clock_enable ? writer_ram_addr : gc_ram_addr;
+   wire [15:0] ram_di = reader_active ? reader_ram_di : gc_ram_di;
    wire [15:0] ram_do;
 
+   reg 		   writer_clock_enable = 0;
+   wire		   writer_finished;
+   reg 		   will_stop_writer = 0;
+   reg 		   writer_started = 0;
+
    GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do), .result(result));
 
-   GC gc (.clk(clk), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(ram_we), .ram_addr(ram_addr), .ram_di(ram_di), .ram_do(ram_do));
+   GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do));
+
+   EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
 
-   EVAL eval (.clk(clk), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
+   READER reader (.clk(clk), .clk_enable(!initial_reset), .uart_rx_byte(uart_rx_byte), .uart_rx_signal(uart_rx_signal), .uart_is_receiving(uart_is_receiving), .active(reader_active), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
+
+   WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .uart_tx_byte(uart_tx_byte), .uart_tx_signal(uart_tx_signal), .uart_is_transmitting(uart_is_transmitting), .finished(writer_finished), .result(result));
 
    // UART outputs
    wire       uart_rx_signal;
@@ -68,36 +98,31 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
    wire       uart_is_transmitting;
    wire       uart_rx_error;
 
-   // Input logic
-   wire [3:0] fifo_in;
-   wire [3:0] fifo_out;
-   wire 	  fifo_full;
-   wire 	  fifo_empty;
-   wire 	  fifo_re = 0;//eval_clock & inst == `INST_READ & !fifo_empty;
-   wire 	  fifo_we = uart_rx_signal & !fifo_full;
-
-   ascii_to_hex a2h (.ascii({1'b0, uart_rx_byte[6:0]}), .hex(fifo_in));
-
-   generic_fifo_sc_a #(.dw(4), .aw(4)) fifo
-    (.clk(clk),
-     .rst(1'b1),
-     .re(fifo_re),
-     .we(fifo_we),
-     .din(fifo_in),
-     .dout(fifo_out),
-     .full(fifo_full),
-     .empty(fifo_empty));
-
    // UART logic
-   reg       uart_tx_signal = 1;
-   wire [7:0] uart_tx_byte = result[7:0];
+   wire 	  uart_tx_signal;
+   wire [7:0] uart_tx_byte;
+
+   always @ (posedge clk) begin
+	  if(writer_finished)
+		will_stop_writer <= 1;
+	  if(will_stop_writer)
+		writer_clock_enable <= 0;
+
+	  if(reader_active) begin
+		 writer_started <= 0;
+		 will_stop_writer <= 0;
+	  end else if(eostate == 5'd7 && !writer_started) begin
+		 writer_started <= 1;
+		 writer_clock_enable <= 1;
+	  end
+   end
 
    // 300 baud uart
-   uart #(.CLOCK_DIVIDE(39)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
+   uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
 
    // Assign the outputs
-   assign led[0] = eval_clock;
+   assign led[0] = eval_clock_enable;
    assign led[1] = uart_is_transmitting;
    assign led[2] = uart_is_receiving;
-   assign led[3] = recv_error;
+   assign led[3] = writer_clock_enable;
 endmodule
diff --git a/reader.v b/reader.v
new file mode 100644
index 0000000..8386b53
--- /dev/null
+++ b/reader.v
@@ -0,0 +1,55 @@
+`define STATE_IDLE    2'd0
+`define STATE_LENGTH  2'd1
+`define STATE_READ1   2'd2
+`define STATE_READ2   2'd3
+
+module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart_rx_signal, input uart_is_receiving, output reg active, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
+   reg [1:0] state = `STATE_IDLE;
+
+   reg [12:0] bytes_left = 0;
+   reg [12:0] current_index = 0;
+
+   assign ram_addr = current_index;
+
+   always @ (posedge clk)
+	 if (clk_enable) begin
+		if(!uart_rx_signal) ram_we <= 0;
+
+		case(state)
+		  `STATE_IDLE: begin
+			 if(uart_rx_signal) begin
+				bytes_left[12:8] <= uart_rx_byte[4:0];
+				bytes_left[7:0] <= 0;
+				current_index <= -1;
+				active <= 1;
+				state <= `STATE_LENGTH;
+			 end else
+			   active <= 0;
+		  end
+
+		  `STATE_LENGTH: begin
+			 if(uart_rx_signal) begin
+				bytes_left[7:0] <= uart_rx_byte;
+				state <= `STATE_READ1;
+			 end
+		  end
+
+		  `STATE_READ1: begin
+			 if(uart_rx_signal) begin
+				ram_di[15:8] <= uart_rx_byte;
+				current_index <= current_index + 1;
+				bytes_left <= bytes_left - 1;
+				state <= `STATE_READ2;
+			 end
+		  end
+
+		  `STATE_READ2: begin
+			 if(uart_rx_signal) begin
+				ram_di[7:0] <= uart_rx_byte;
+				ram_we <= 1;
+				state <= |bytes_left ? `STATE_READ1 : `STATE_IDLE;
+			 end
+		  end
+		endcase
+	 end
+endmodule
diff --git a/writer.v b/writer.v
new file mode 100644
index 0000000..7ef47ff
--- /dev/null
+++ b/writer.v
@@ -0,0 +1,62 @@
+`define STATE_WRITE_TYPE 3'd0
+`define STATE_WRITE1     3'd1
+`define STATE_WRITE2     3'd2
+`define STATE_WRITE3     3'd3
+`define STATE_WRITE4     3'd4
+
+module WRITER (input clk, input clk_enable, output [7:0] uart_tx_byte, output reg uart_tx_signal = 0, input uart_is_transmitting, output reg finished = 0, input [15:0] result);
+   reg [2:0] state = `STATE_WRITE_TYPE;
+   reg [3:0] tx_hex = 0;
+
+   hex_to_ascii h2a (.hex(tx_hex), .ascii(uart_tx_byte));
+
+   always @ (posedge clk)
+	 if (clk_enable) begin
+		if(uart_tx_signal)
+		  uart_tx_signal <= 0;
+
+		case(state)
+		  `STATE_WRITE_TYPE: begin
+			 finished <= 0;
+			 if(!uart_is_transmitting && !uart_tx_signal) begin
+				uart_tx_signal <= 1;
+				tx_hex <= {1'b0, result[15:13]};
+				state <= `STATE_WRITE1;
+			 end
+		  end
+
+		  `STATE_WRITE1: begin
+			 if(!uart_is_transmitting && !uart_tx_signal) begin
+				uart_tx_signal <= 1;
+				tx_hex <= {3'b0, result[12]};
+				state <= `STATE_WRITE2;
+			 end
+		  end
+
+		  `STATE_WRITE2: begin
+			 if(!uart_is_transmitting && !uart_tx_signal) begin
+				uart_tx_signal <= 1;
+				tx_hex <= result[11:8];
+				state <= `STATE_WRITE3;
+			 end
+		  end
+
+		  `STATE_WRITE3: begin
+			 if(!uart_is_transmitting && !uart_tx_signal) begin
+				uart_tx_signal <= 1;
+				tx_hex <= result[7:4];
+				state <= `STATE_WRITE4;
+			 end
+		  end
+
+		  `STATE_WRITE4: begin
+			 if(!uart_is_transmitting && !uart_tx_signal) begin
+				uart_tx_signal <= 1;
+				tx_hex <= result[3:0];
+				finished <= 1;
+				state <= `STATE_WRITE_TYPE;
+			 end
+		  end
+		endcase
+	 end
+endmodule