From: Marius Gavrilescu <marius@ieval.ro>
Date: Mon, 19 Feb 2018 13:48:32 +0000 (+0000)
Subject: Pull the gcram outside the gc
X-Git-Url: http://git.ieval.ro/?a=commitdiff_plain;h=44b73af51bca05eb26fd1557a192eed779fc065e;p=yule.git

Pull the gcram outside the gc
---

diff --git a/gc.v b/gc.v
index ceae7d7..d452178 100644
--- a/gc.v
+++ b/gc.v
@@ -1,6 +1,6 @@
 `include "gcram.v"
 
-module GC (input clk, input mclk, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output [15:0] result);
+module GC (input clk, input mclk, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do);
    reg [15:0] rom_output;
    reg [5:0]  gostate = 6'o0;
    reg [5:0]  gnstate;
@@ -12,7 +12,7 @@ module GC (input clk, input mclk, input [15:0] Ein, output [15:0] Eout, input [3
 
    wire ga_zero_disp = rom_output[15];
    wire gcop_disp    = rom_output[14];
-   wire write        = rom_output[13];
+   assign ram_we     = rom_output[13];
    wire adr          = rom_output[12];
    wire rdR          = rom_output[11];
    wire rdQ          = rom_output[10];
@@ -99,7 +99,8 @@ module GC (input clk, input mclk, input [15:0] Ein, output [15:0] Eout, input [3
 
    reg [12:0] A; // latched address
 
-   wire [15:0] I;
+   assign ram_addr = A;
+   assign ram_di = S;
 
    wire [15:0] G;
    wire [15:0] Gout;
@@ -108,7 +109,7 @@ module GC (input clk, input mclk, input [15:0] Ein, output [15:0] Eout, input [3
    wire [15:0] GfromQ = rdQ ? Q : 0;
    wire [15:0] GfromP = rdP ? {3'b0, P} : 0;
    wire [15:0] GfromP_plus = rdP_plus ? {3'b0, P + 1} : 0;
-   wire [15:0] GfromI = conn_i ? I : 0;
+   wire [15:0] GfromI = conn_i ? ram_do : 0;
    wire [12:0] GAfromE = conn_ea ? Ein_latched[12:0] : 0;
    wire [2:0] GTfromE = conn_et ? Ein_latched[15:13] : 0;
    wire [15:0] GfromE = {GTfromE, GAfromE};
@@ -119,8 +120,6 @@ module GC (input clk, input mclk, input [15:0] Ein, output [15:0] Eout, input [3
    assign Eout[12:0]  = conn_ea ? Gout[12:0]  : 0;
    assign Eout[15:13] = conn_et ? Gout[15:13] : 0;
 
-   GCRAM gcram (.clk(mclk), .we(write), .addr(A), .do(I), .di(S), .result(result));
-
    always @ (posedge clk) begin
 	  if (ldS) S = G;
 	  if (ldP) P <= G[12:0];
diff --git a/lisp_processor.v b/lisp_processor.v
index 827fbc7..7be974b 100644
--- a/lisp_processor.v
+++ b/lisp_processor.v
@@ -50,7 +50,14 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
 
    wire 	  step_eval;
 
-   GC gc (.clk(gc_clock), .mclk(clk), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .result(result));
+   wire        ram_we;
+   wire [12:0] ram_addr;
+   wire [15:0] ram_di;
+   wire [15:0] ram_do;
+
+   GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do), .result(result));
+
+   GC gc (.clk(gc_clock), .mclk(clk), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(ram_we), .ram_addr(ram_addr), .ram_di(ram_di), .ram_do(ram_do));
 
    EVAL eval (.clk(eval_clock), .mclk(clk), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));