From a051754e2f539c6ed180e93ecf31cdcb95950896 Mon Sep 17 00:00:00 2001 From: Marius Gavrilescu Date: Mon, 4 Dec 2017 12:44:54 +0200 Subject: [PATCH 1/1] Initial commit --- .gitignore | 10 + Makefile | 25 + asciihex.v | 48 + flash.pcf | 33 + flash.txt | 4224 +++++++++++++++++++++++++++++++++++++++++++ flash.v | 96 + gc.v | 153 ++ generic_dpram.v | 503 ++++++ generic_fifo_sc_a.v | 335 ++++ iCEburn.py | 75 + libiceblink.py | 376 ++++ multiple_trigger.v | 20 + prescaler.v | 15 + processor_32.v | 219 +++ processor_4.v | 264 +++ ram.v | 22 + rom.v | 28 + single_trigger.v | 23 + to-philippa.zip | Bin 0 -> 36284 bytes uart.v | 213 +++ yosys-sim-script | 3 + 21 files changed, 6685 insertions(+) create mode 100644 .gitignore create mode 100644 Makefile create mode 100644 asciihex.v create mode 100644 flash.pcf create mode 100644 flash.txt create mode 100644 flash.v create mode 100644 gc.v create mode 100644 generic_dpram.v create mode 100644 generic_fifo_sc_a.v create mode 100755 iCEburn.py create mode 100644 libiceblink.py create mode 100644 multiple_trigger.v create mode 100644 prescaler.v create mode 100644 processor_32.v create mode 100644 processor_4.v create mode 100644 ram.v create mode 100644 rom.v create mode 100644 single_trigger.v create mode 100644 to-philippa.zip create mode 100644 uart.v create mode 100755 yosys-sim-script diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..5803134 --- /dev/null +++ b/.gitignore @@ -0,0 +1,10 @@ +tools/ +to-phillippa.zip +__pycache__ +\#* +.#* +test.vcd +flash.blif +flash.bin +flash.asc +flash.rpt diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..f26533b --- /dev/null +++ b/Makefile @@ -0,0 +1,25 @@ +PROJ = flash +PIN_DEF = flash.pcf +DEVICE = hx1k + +all: $(PROJ).rpt $(PROJ).bin + +%.blif: %.v + yosys -p 'synth_ice40 -top top -blif $@' $< + +%.asc: $(PIN_DEF) %.blif + arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P vq100 + +%.bin: %.asc + icepack $< $@ + +%.rpt: %.asc + icetime -d $(DEVICE) -mtr $@ $< + +prog: $(PROJ).bin + ./iCEburn.py -e -v -w $< + +clean: + rm -f $(PROJ).blif $(PROJ).asc $(PROJ).bin + +.PHONY: all prog clean diff --git a/asciihex.v b/asciihex.v new file mode 100644 index 0000000..cfd4487 --- /dev/null +++ b/asciihex.v @@ -0,0 +1,48 @@ +// convert ASCII 0-9A-Za-z to/from numbers + +module ascii_to_hex(input [7:0] ascii, output [3:0] hex); + wire [7:0] hex8; + assign hex8 = + ascii > 8'd47 & ascii < 8'd58 ? ascii - 8'd48 : + ascii > 8'd64 & ascii < 8'd71 ? ascii - 8'd55 : + ascii > 8'd96 & ascii < 8'd103 ? ascii - 8'd87 : 8'bxxxx; + assign hex = hex8[3:0]; + +/* assign hex = + ascii == 8'd48 ? 4'd0 : + ascii == 8'd49 ? 4'd1 : + ascii == 8'd50 ? 4'd2 : + ascii == 8'd51 ? 4'd3 : + ascii == 8'd52 ? 4'd4 : + ascii == 8'd53 ? 4'd5 : + ascii == 8'd54 ? 4'd6 : + ascii == 8'd55 ? 4'd7 : + ascii == 8'd56 ? 4'd8 : + ascii == 8'd57 ? 4'd9 : + ascii == 8'd65 ? 4'd10 : + ascii == 8'd66 ? 4'd11 : + ascii == 8'd67 ? 4'd12 : + ascii == 8'd68 ? 4'd13 : + ascii == 8'd69 ? 4'd14 : 4'd15;*/ +endmodule // ascii_to_hex + +module hex_to_ascii(input [3:0] hex, output [7:0] ascii); +// assign ascii = hex < 4'd10 ? 8'd48 + hex : 8'd55 + hex; + assign ascii = + hex == 4'd0 ? 8'd48 : + hex == 4'd1 ? 8'd49 : + hex == 4'd2 ? 8'd50 : + hex == 4'd3 ? 8'd51 : + hex == 4'd4 ? 8'd52 : + hex == 4'd5 ? 8'd53 : + hex == 4'd6 ? 8'd54 : + hex == 4'd7 ? 8'd55 : + hex == 4'd8 ? 8'd56 : + hex == 4'd9 ? 8'd57 : + hex == 4'd10 ? 8'd65 : + hex == 4'd11 ? 8'd66 : + hex == 4'd12 ? 8'd67 : + hex == 4'd13 ? 8'd68 : + hex == 4'd14 ? 8'd69 : + hex == 4'd15 ? 8'd70 : 8'bx; +endmodule // hex_to_ascii diff --git a/flash.pcf b/flash.pcf new file mode 100644 index 0000000..7426699 --- /dev/null +++ b/flash.pcf @@ -0,0 +1,33 @@ + +set_io OUT_R[0] 72 +set_io OUT_R[1] 69 +set_io OUT_R[2] 66 + +set_io OUT_C[0] 87 +set_io OUT_C[1] 85 +set_io OUT_C[2] 82 +set_io OUT_C[3] 80 +set_io OUT_C[4] 78 +set_io OUT_C[5] 73 +set_io OUT_C[6] 71 +set_io OUT_C[7] 68 + +set_io IND[0] 86 +set_io IND[1] 83 +set_io IND[2] 81 +set_io IND[3] 79 + +set_io IN_R[0] 100 +set_io IN_R[1] 15 +set_io IN_R[2] 16 +set_io IN_R[3] 19 + +set_io IN_C[0] 90 +set_io IN_C[1] 93 +set_io IN_C[2] 95 +set_io IN_C[3] 97 + +set_io CLK 13 + +set_io UART_TX 10 +set_io UART_RX 9 \ No newline at end of file diff --git a/flash.txt b/flash.txt new file mode 100644 index 0000000..9d1272a --- /dev/null +++ b/flash.txt @@ -0,0 +1,4224 @@ +.comment arachne-pnr 0.1+154+0 (git sha1 6b83364, g++ 4.8.4-2ubuntu1~14.04.1 -O2) +.device 1k +.io_tile 1 0 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000100000000000000 +000000000000000000 +000000000000000000 +000100000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +.io_tile 2 0 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 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+ always @ (negedge counter[13]) begin + + shift_in <= { shift_in[2:0], shift_in[3] }; + + end + + assign IN_C = shift_in; + + reg [15:0] buttons = 0; + + always @ (posedge counter[13]) begin + + case (shift_in) + 4'b1110: begin + buttons[0] <= !IN_R[0]; + buttons[4] <= !IN_R[1]; + buttons[8] <= !IN_R[2]; + buttons[12] <= !IN_R[3]; + end + 4'b1101: begin + buttons[1] <= !IN_R[0]; + buttons[5] <= !IN_R[1]; + buttons[9] <= !IN_R[2]; + buttons[13] <= !IN_R[3]; + end + 4'b1011: begin + buttons[2] <= !IN_R[0]; + buttons[6] <= !IN_R[1]; + buttons[10] <= !IN_R[2]; + buttons[14] <= !IN_R[3]; + end + 4'b0111: begin + buttons[3] <= !IN_R[0]; + buttons[7] <= !IN_R[1]; + buttons[11] <= !IN_R[2]; + buttons[15] <= !IN_R[3]; + end + endcase + + end + + // Connect up the processor + + PROCESSOR cpu(.clk(CLK),//counter[20]), + .led(led), + .indicators(IND), + .uart_tx(UART_TX), + .uart_rx(UART_RX), + .buttons(buttons)); + + // Handle output stuff + + reg [7:0] out; + + reg [2:0] shift_out = 3'b001; + + always @ (posedge counter[7]) begin + + if (shift_out[2] == 1) + out <= led[7:0]; + if (shift_out[0] == 1) + out <= led[15:8]; + if (shift_out[1] == 1) + out <= led[23:16]; + + shift_out <= { shift_out[1:0], shift_out[2] }; + + end + + assign OUT_R = shift_out; + + assign OUT_C = out; + +endmodule + + diff --git a/gc.v b/gc.v new file mode 100644 index 0000000..b840205 --- /dev/null +++ b/gc.v @@ -0,0 +1,153 @@ +module GC (input clk, input mclk, input [7:0] Ein, output [7:0] Eout, input [3:0] gcop, output [5:0] ostate, output step_eval); + reg [5:0] gostate = 6'o2; + reg [5:0] gnstate; + reg [16:0] rom_output; + reg [7:0] Ein_latched; + + always @(posedge clk) begin + Ein_latched <= Ein; + end + + wire ga_zero_disp = rom_output[15]; + wire gcop_disp = rom_output[14]; + wire write = rom_output[13]; + wire adr = rom_output[12]; + wire rdR = rom_output[11]; + wire rdQ = rom_output[10]; + wire rdP_plus = rom_output[9]; + wire rdP = rom_output[8]; + wire ldS = rom_output[7]; + wire ldR = rom_output[6]; + wire ldQ = rom_output[5]; + wire ldP = rom_output[4]; + wire conn_i = rom_output[3]; + wire conn_et = rom_output[2]; + wire conn_ea = rom_output[1]; + assign step_eval = rom_output[0]; + + wire ga_zero = ~|G[7:5]; + + always @* begin + case(gostate) + 6'o00: begin rom_output <= 16'o010242; gnstate <= 6'o01; end + 6'o01: begin rom_output <= 16'o000031; gnstate <= 6'o02; end + 6'o02: begin rom_output <= 16'o040000; gnstate <= 6'o20; end + 6'o03: begin rom_output <= 16'o000126; gnstate <= 6'o04; end + 6'o04: begin rom_output <= 16'o001200; gnstate <= 6'o05; end + 6'o05: begin rom_output <= 16'o002020; gnstate <= 6'o06; end + 6'o06: begin rom_output <= 16'o000051; gnstate <= 6'o02; end + 6'o07: begin rom_output <= 16'o002020; gnstate <= 6'o10; end + 6'o10: begin rom_output <= 16'o001200; gnstate <= 6'o11; end + 6'o11: begin rom_output <= 16'o004020; gnstate <= 6'o12; end + 6'o12: begin rom_output <= 16'o002100; gnstate <= 6'o13; end + 6'o13: begin rom_output <= 16'o000057; gnstate <= 6'o02; end + 6'o14: begin rom_output <= 16'o004020; gnstate <= 6'o04; end + 6'o15: begin rom_output <= 16'o000246; gnstate <= 6'o16; end + 6'o16: begin rom_output <= 16'o020001; gnstate <= 6'o02; end + 6'o17: begin rom_output <= 16'o002100; gnstate <= 6'o42; end + 6'o20: begin rom_output <= 16'o000001; gnstate <= 6'o02; end + 6'o21: begin rom_output <= 16'o010306; gnstate <= 6'o06; end + 6'o22: begin rom_output <= 16'o000440; gnstate <= 6'o03; end + 6'o23: begin rom_output <= 16'o012200; gnstate <= 6'o12; end + 6'o24: begin rom_output <= 16'o000500; gnstate <= 6'o07; end + 6'o25: begin rom_output <= 16'o004040; gnstate <= 6'o24; end + 6'o26: begin rom_output <= 16'o014200; gnstate <= 6'o06; end + 6'o27: begin rom_output <= 16'o000440; gnstate <= 6'o14; end + 6'o30: begin rom_output <= 16'o012300; gnstate <= 6'o06; end + 6'o31: begin rom_output <= 16'o111300; gnstate <= 6'o44; end + 6'o32: begin rom_output <= 16'o111300; gnstate <= 6'o40; end + 6'o33: begin rom_output <= 16'o014200; gnstate <= 6'o15; end + 6'o34: begin rom_output <= 16'o000047; gnstate <= 6'o02; end + 6'o35: begin rom_output <= 16'o002007; gnstate <= 6'o02; end + 6'o36: begin rom_output <= 16'o002003; gnstate <= 6'o02; end + 6'o37: begin rom_output <= 16'o014200; gnstate <= 6'o55; end + 6'o40: begin rom_output <= 16'o004020; gnstate <= 6'o17; end + 6'o41: begin rom_output <= 16'o000000; gnstate <= 6'o41; end + 6'o42: begin rom_output <= 16'o000206; gnstate <= 6'o47; end + 6'o43: begin rom_output <= 16'o000106; gnstate <= 6'o46; end + 6'o44: begin rom_output <= 16'o004020; gnstate <= 6'o43; end + 6'o45: begin rom_output <= 16'o000000; gnstate <= 6'o41; end + 6'o46: begin rom_output <= 16'o002200; gnstate <= 6'o47; end + 6'o47: begin rom_output <= 16'o020440; gnstate <= 6'o50; end + 6'o50: begin rom_output <= 16'o111200; gnstate <= 6'o52; end + 6'o51: begin rom_output <= 16'o021100; gnstate <= 6'o54; end + 6'o52: begin rom_output <= 16'o004200; gnstate <= 6'o51; end + 6'o53: begin rom_output <= 16'o000000; gnstate <= 6'o41; end + 6'o54: begin rom_output <= 16'o004021; gnstate <= 6'o02; end + 6'o55: begin rom_output <= 16'o002100; gnstate <= 6'o56; end + 6'o56: begin rom_output <= 16'o000050; gnstate <= 6'o57; end + 6'o57: begin rom_output <= 16'o004007; gnstate <= 6'o02; end + default: begin rom_output <= 16'o040000; gnstate <= 6'o20; end + endcase; // case (gostate) + end // always @ (posedge mclk) + + always @ (posedge clk) begin + gostate <= + /* ga_zero_disp ? (gnstate | ga_zero) : */ + gcop_disp ? (gnstate | gcop) : + gnstate; + end // always @ (posedge clk) + + assign ostate = gostate; + + reg [4:0] P = 5'b0; // free storage pointer begins at 0 + reg [7:0] Q; + reg [7:0] R; + reg [7:0] S; + + reg [4:0] A; // latched address + + wire [7:0] I; + + wire [7:0] G; + + /* + assign G = rdR ? R : 8'bzzzzzzzz; + assign G = rdQ ? Q : 8'bzzzzzzzz; + assign G = rdP ? {3'b0, P} : 8'bzzzzzzzz; + assign G = rdP_plus ? {3'b0, P+1} : 8'bzzzzzzzz; + assign G = conn_i ? I : 8'bzzzzzzzz; + assign G[4:0] = conn_ea ? E[4:0] : 5'bzzzzz; + assign G[7:5] = conn_et ? E[7:5] : 3'bzzz; + + assign E[4:0] = conn_ea ? G[4:0] : 5'bzzzzz; + assign E[7:5] = conn_et ? G[7:5] : 3'bzzz; + */ + + wire [7:0] GfromR = rdR ? R : 0; + wire [7:0] GfromQ = rdQ ? Q : 0; + wire [7:0] GfromP = rdP ? {3'b0, P} : 0; + wire [7:0] GfromP_plus = rdP_plus ? {3'b0, P + 1} : 0; + wire [7:0] GfromI = conn_i ? I : 0; + wire [4:0] GAfromE = conn_ea ? Ein_latched[4:0] : 0; + wire [3:0] GTfromE = conn_et ? Ein_latched[7:5] : 0; + wire [7:0] GfromE = {GTfromE, GAfromE}; + + assign G = GfromR | GfromQ | GfromP | GfromP_plus | GfromI | GfromE; + + assign Eout[4:0] = conn_ea ? G[4:0] : 0; + assign Eout[7:5] = conn_et ? G[7:5] : 0; + + generic_dpram #(.aw(5), .dw(8)) RAM + ( .rclk(mclk), + .wclk(mclk), + .rrst(1'b0), + .wrst(1'b0), + .rce(1'b1), + .wce(1'b1), + + .oe(1'b1), + .we(write), + .raddr(A), + .waddr(A), + .do(I), + .di(S)); + + always @ (posedge clk) begin + if (ldS) S = G; + if (ldP) P <= G[4:0]; + if (ldR) R <= G; + if (ldQ) Q <= G; + if (adr) A <= S[4:0]; + end +endmodule // GC diff --git a/generic_dpram.v b/generic_dpram.v new file mode 100644 index 0000000..ca0fced --- /dev/null +++ b/generic_dpram.v @@ -0,0 +1,503 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Dual-Port Synchronous RAM //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/generic_memories/ //// +//// //// +//// Description //// +//// This block is a wrapper with common dual-port //// +//// synchronous memory interface for different //// +//// types of ASIC and FPGA RAMs. Beside universal memory //// +//// interface it also provides behavioral model of generic //// +//// dual-port synchronous RAM. //// +//// It also contains a fully synthesizeable model for FPGAs. //// +//// It should be used in all OPENCORES designs that want to be //// +//// portable accross different target technologies and //// +//// independent of target memory. //// +//// //// +//// Supported ASIC RAMs are: //// +//// - Artisan Dual-Port Sync RAM //// +//// - Avant! Two-Port Sync RAM (*) //// +//// - Virage 2-port Sync RAM //// +//// //// +//// Supported FPGA RAMs are: //// +//// - Generic FPGA (VENDOR_FPGA) //// +//// Tested RAMs: Altera, Xilinx //// +//// Synthesis tools: LeonardoSpectrum, Synplicity //// +//// - Xilinx (VENDOR_XILINX) //// +//// - Altera (VENDOR_ALTERA) //// +//// //// +//// To Do: //// +//// - fix Avant! //// +//// - add additional RAMs (VS etc) //// +//// //// +//// Author(s): //// +//// - Richard Herveille, richard@asics.ws //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2001/11/08 19:11:31 samg +// added valid checks to behvioral model +// +// Revision 1.1.1.1 2001/09/14 09:57:10 rherveille +// Major cleanup. +// Files are now compliant to Altera & Xilinx memories. +// Memories are now compatible, i.e. drop-in replacements. +// Added synthesizeable generic FPGA description. +// Created "generic_memories" cvs entry. +// +// Revision 1.1.1.2 2001/08/21 13:09:27 damjan +// *** empty log message *** +// +// Revision 1.1 2001/08/20 18:23:20 damjan +// Initial revision +// +// Revision 1.1 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.2 2001/07/30 05:38:02 lampret +// Adding empty directories required by HDL coding guidelines +// +// + +//`include "timescale.v" + +`define VENDOR_FPGA +//`define VENDOR_XILINX +//`define VENDOR_ALTERA + +module generic_dpram( + // Generic synchronous dual-port RAM interface + rclk, rrst, rce, oe, raddr, do, + wclk, wrst, wce, we, waddr, di +); + + // + // Default address and data buses width + // + parameter aw = 5; // number of bits in address-bus + parameter dw = 16; // number of bits in data-bus + + // + // Generic synchronous double-port RAM interface + // + // read port + input rclk; // read clock, rising edge trigger + input rrst; // read port reset, active high + input rce; // read port chip enable, active high + input oe; // output enable, active high + input [aw-1:0] raddr; // read address + output [dw-1:0] do; // data output + + // write port + input wclk; // write clock, rising edge trigger + input wrst; // write port reset, active high + input wce; // write port chip enable, active high + input we; // write enable, active high + input [aw-1:0] waddr; // write address + input [dw-1:0] di; // data input + + // + // Module body + // + +`ifdef VENDOR_FPGA + // + // Instantiation synthesizeable FPGA memory + // + // This code has been tested using LeonardoSpectrum and Synplicity. + // The code correctly instantiates Altera EABs and Xilinx BlockRAMs. + // + + reg [dw-1 :0] mem [(1<= (n-1) ) & !re) empty_n_r <= #1 1'b0; + else + if(re & (cnt <= n ) & !we) empty_n_r <= #1 1'b1; + +always @(posedge clk `SC_FIFO_ASYNC_RESET) + if(!rst) full_n_r <= #1 1'b0; + else + if(clr) full_n_r <= #1 1'b0; + else + if(we & (cnt >= (max_size-n) ) & !re) full_n_r <= #1 1'b1; + else + if(re & (cnt <= (max_size-n+1)) & !we) full_n_r <= #1 1'b0; + +//////////////////////////////////////////////////////////////////// +// +// Sanity Check +// + +// synopsys translate_off +always @(posedge clk) + if(we & full) + $display("%m WARNING: Writing while fifo is FULL (%t)",$time); + +always @(posedge clk) + if(re & empty) + $display("%m WARNING: Reading while fifo is EMPTY (%t)",$time); +// synopsys translate_on +endmodule diff --git a/iCEburn.py b/iCEburn.py new file mode 100755 index 0000000..5a75c4d --- /dev/null +++ b/iCEburn.py @@ -0,0 +1,75 @@ +#!/usr/bin/python3 +import argparse +from libiceblink import ICE40Board, M25P10 + +def main(): + ap = argparse.ArgumentParser() + ap.add_argument("-e", "--erase", action="store_true") + ap.add_argument("-v", "--verbose", action="store_true") + ap.add_argument("-w", "--write", type=argparse.FileType("rb")) + args = ap.parse_args() + + board = ICE40Board() + + if args.verbose: + print("Found iCE40 board serial: %s" % board.get_serial()) + + + sp = board.get_spi_port(0) + + with board.get_gpio() as gpio: + # Force the FPGA into reset so we may drive the IOs + gpio.ice40SetReset(True) + + with board.get_spi_port(0) as sp: + sp.setSpeed(50000000) + sp.setMode() + + flash = M25P10(sp.io) + + flash.wakeup() + + # Verify that we're talking to the part we think we are + assert flash.getID() == b'\x20\x20\x11' + + # Now, do the actions + if args.erase: + if args.verbose: + print("Erasing flash...") + flash.chipErase() + if args.verbose: + print("") + + if args.write: + data = args.write.read() + + if args.verbose: + print("Writing image...") + + for addr in range(0, len(data), 256): + buf = data[addr:addr+256] + flash.pageProgram(addr, buf) + + if args.verbose: + print("Verifying written image...") + # Now verify + buf = flash.read(0, len(data)) + assert len(buf) == len(data) + + nvfailures = 0 + for i,(a,b) in enumerate(zip(buf, data)): + if a!=b: + print ("verification failure at %06x: %02x != %02x" % + (i,a,b)) + nvfailures += 1 + + if nvfailures == 5: + print("Too many verification failures, bailing") + break + + # Release the FPGA reset + gpio.ice40SetReset(False) + + +if __name__ == "__main__": + main() diff --git a/libiceblink.py b/libiceblink.py new file mode 100644 index 0000000..6cdfe1e --- /dev/null +++ b/libiceblink.py @@ -0,0 +1,376 @@ +import usb.core +import usb.util +import array +import struct +import binascii +import time + +class ProtocolError(Exception): + pass + +class SPIProtocolError(Exception): + def __init__(self, cmd, rescode): + lut = { + 3: "Resource in use", + 4: "Resource not opened", + 12: "Invalid enum" + } + if rescode in lut: + err = lut[rescode] + else: + err = "error code %d" % rescode + + ProtocolError.__init__(self, "Command %s failed with error: %s" %( cmd, + err)) + +class M25P10(object): + STAT_BUSY = 0x1 + STAT_WEL = 0x2 + + CMD_GET_STATUS = 0x05 + CMD_WRITE_ENABLE = 0x6 + CMD_READ_ID = 0x9F + CMD_WAKEUP = 0xAB + CMD_CHIP_ERASE = 0xC7 + CMD_PAGE_PROGRAM = 0x02 + CMD_FAST_READ = 0xB + + def __init__(self, iofn): + self.io = iofn + + def wakeup(self): + self.io([self.CMD_WAKEUP]) + + def setWritable(self): + self.io([self.CMD_WRITE_ENABLE]) + + def chipErase(self): + self.setWritable() + self.io([self.CMD_CHIP_ERASE]) + self.waitDone() + + def read(self, addr, size): + return self.io([self.CMD_FAST_READ, (addr>>16) & 0xFF, (addr>>8)&0xFF, addr & + 0xFF, 0x00], size+5)[5:] + def pageProgram(self, addr, buf): + self.setWritable() + assert len(buf) <= 256 + assert addr & 0xFF == 0 + + self.io([self.CMD_PAGE_PROGRAM, (addr>>16) & 0xFF, (addr>>8)&0xFF, addr & + 0xFF] + list(buf)) + self.waitDone() + + def waitDone(self): + while self.getStatus() & self.STAT_BUSY: + pass + + def getStatus(self): + return self.io([self.CMD_GET_STATUS],2)[1] + + def getID(self): + return self.io([self.CMD_READ_ID],4)[1:] + + +class ICE40Board(object): + + CMD_GET_BOARD_TYPE = 0xE2 + CMD_GET_BOARD_SERIAL = 0xE4 + + class __ICE40BoardComm(object): + def __init__(self, dev): + self.__is_open = False + self.dev = dev + + def __enter__(self): + self.open() + return self + + def __exit__(self, type, err, traceback): + self.__cleanup() + + def __del__(self): + self.__cleanup() + + def __cleanup(self): + if self.__is_open: + self.close() + + def open(self): + assert not self.__is_open + self.dev.checked_cmd(0x04, 0x00, "bcommopen", [0x00], noret=True) + self.__is_open = True + + def close(self): + assert self.__is_open + self.dev.checked_cmd(0x04, 0x01, "bcommclose", [0x00], noret=True, + ) + self.__is_open = False + + def __check_counts(self, status, resb, wr, rd): + if status & 0x80: + wb = struct.unpack('M zWA;AA91%0xm~xW9KOh1A`DEzYO8!0gUpsIBYyew(8*?KAM_MIC2ms&%Zy5E>@6E{- z3IOoOF)#qY-<{ky0x|#)060MEH-aZna9=GT0DvGU0082DLC|wBFf%hXa;0(pi?#iY z^UwC*u!0gLe+AIN`%WFGoR63{0Q&{%DDye*!9N*uDpRnj)SOTBHL zfJ#DJ;i_z3-VJJ|xuL?Xlnfo{a|*M$sfHEPy>Y~mlMmX+AVFFh3Fme$ID5pro3Ge) zL5r7iDZ3nZsLFm*aV$$cRqSjAQ5$q<&jDGy>WG}Y)=9`4>+GJdd=xE(QJ{JrFuK!b z$W^msz{9wcLNyhU5@EiR9%O=&LNynW9%MEkjbMV3Mzt6On~X-of*ltJuk~XOi?KAF z1X!8Y`eg|0BAu$g-Y2U)TU9@nYyS!O@7{N1UuiGG2LM?20suhxFWxt{)N?SU(KoaH zPtHHrfOAw_Nb7p)WM#A=O&9?lq7%c^8HN{4KjqU0Plbu`6+^LA=hiBviVO{<8bxkH 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z1rPwB121SbM;AzdFTls28=8M!{zXIjlmUJHrwqsgFsQHga|JE%dCZ0IKeW%U0QtWB zztME<^-WDp3|;=Q=KJJs|97qn+e&*89st0)=RYz?{BJG)!R7s2tN(8;jVyHSO=$E? zt^O|d&m_4+#{5|ZSk>7vEnv?%K_Mbwu zzlZ%ZmhA6X8@hkT{_PI?Gs5TZ&~J=?LI001srWnccV*(=1OF-P`yH&S|65)EP3HIa*nbKRerFS#|KHgElpp*(^q(g;zoS{~ z{vYUno#XsH{GSHQ-|^ATf8qbfocZ^Ve;VU{N20j?hWwXl?(ZT0v={x39CZ5&`F~oE p{vQ2LYsv3)5|6*=|7$z>e=$KmXX1YZSw;o8{FIM22ma&R{|ELM$F~3g literal 0 HcmV?d00001 diff --git a/uart.v b/uart.v new file mode 100644 index 0000000..6db3650 --- /dev/null +++ b/uart.v @@ -0,0 +1,213 @@ +`timescale 1ns / 1ps +// Documented Verilog UART +// Copyright (C) 2010 Timothy Goddard (tim@goddard.net.nz) +// Distributed under the MIT licence. +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +module uart( + input clk, // The master clock for this module + input rst, // Synchronous reset. + input rx, // Incoming serial line + output tx, // Outgoing serial line + input transmit, // Signal to transmit + input [7:0] tx_byte, // Byte to transmit + output received, // Indicated that a byte has been received. + output [7:0] rx_byte, // Byte received + output is_receiving, // Low when receive line is idle. + output is_transmitting, // Low when transmit line is idle. + output recv_error // Indicates error in receiving packet. + ); + +parameter CLOCK_DIVIDE = 1302; // clock rate (50Mhz) / (baud rate (9600) * 4) + +// States for the receiving state machine. +// These are just constants, not parameters to override. +parameter RX_IDLE = 0; +parameter RX_CHECK_START = 1; +parameter RX_READ_BITS = 2; +parameter RX_CHECK_STOP = 3; +parameter RX_DELAY_RESTART = 4; +parameter RX_ERROR = 5; +parameter RX_RECEIVED = 6; + +// States for the transmitting state machine. +// Constants - do not override. +parameter TX_IDLE = 0; +parameter TX_SENDING = 1; +parameter TX_DELAY_RESTART = 2; + +reg [10:0] rx_clk_divider = CLOCK_DIVIDE; +reg [10:0] tx_clk_divider = CLOCK_DIVIDE; + +reg [2:0] recv_state = RX_IDLE; +reg [5:0] rx_countdown; +reg [3:0] rx_bits_remaining; +reg [7:0] rx_data; + +reg tx_out = 1'b1; +reg [1:0] tx_state = TX_IDLE; +reg [5:0] tx_countdown; +reg [3:0] tx_bits_remaining; +reg [7:0] tx_data; + +assign received = recv_state == RX_RECEIVED; +assign recv_error = recv_state == RX_ERROR; +assign is_receiving = recv_state != RX_IDLE; +assign rx_byte = rx_data; + +assign tx = tx_out; +assign is_transmitting = tx_state != TX_IDLE; + +always @(posedge clk) begin + if (rst) begin + recv_state = RX_IDLE; + tx_state = TX_IDLE; + end + + // The clk_divider counter counts down from + // the CLOCK_DIVIDE constant. Whenever it + // reaches 0, 1/16 of the bit period has elapsed. + // Countdown timers for the receiving and transmitting + // state machines are decremented. + rx_clk_divider = rx_clk_divider - 1; + if (!rx_clk_divider) begin + rx_clk_divider = CLOCK_DIVIDE; + rx_countdown = rx_countdown - 1; + end + tx_clk_divider = tx_clk_divider - 1; + if (!tx_clk_divider) begin + tx_clk_divider = CLOCK_DIVIDE; + tx_countdown = tx_countdown - 1; + end + + // Receive state machine + case (recv_state) + RX_IDLE: begin + // A low pulse on the receive line indicates the + // start of data. + if (!rx) begin + // Wait half the period - should resume in the + // middle of this first pulse. + rx_clk_divider = CLOCK_DIVIDE; + rx_countdown = 2; + recv_state = RX_CHECK_START; + end + end + RX_CHECK_START: begin + if (!rx_countdown) begin + // Check the pulse is still there + if (!rx) begin + // Pulse still there - good + // Wait the bit period to resume half-way + // through the first bit. + rx_countdown = 4; + rx_bits_remaining = 8; + recv_state = RX_READ_BITS; + end else begin + // Pulse lasted less than half the period - + // not a valid transmission. + recv_state = RX_ERROR; + end + end + end + RX_READ_BITS: begin + if (!rx_countdown) begin + // Should be half-way through a bit pulse here. + // Read this bit in, wait for the next if we + // have more to get. + rx_data = {rx, rx_data[7:1]}; + rx_countdown = 4; + rx_bits_remaining = rx_bits_remaining - 1; + recv_state = rx_bits_remaining ? RX_READ_BITS : RX_CHECK_STOP; + end + end + RX_CHECK_STOP: begin + if (!rx_countdown) begin + // Should resume half-way through the stop bit + // This should be high - if not, reject the + // transmission and signal an error. + recv_state = rx ? RX_RECEIVED : RX_ERROR; + end + end + RX_DELAY_RESTART: begin + // Waits a set number of cycles before accepting + // another transmission. + recv_state = rx_countdown ? RX_DELAY_RESTART : RX_IDLE; + end + RX_ERROR: begin + // There was an error receiving. + // Raises the recv_error flag for one clock + // cycle while in this state and then waits + // 2 bit periods before accepting another + // transmission. + rx_countdown = 8; + recv_state = RX_DELAY_RESTART; + end + RX_RECEIVED: begin + // Successfully received a byte. + // Raises the received flag for one clock + // cycle while in this state. + recv_state = RX_IDLE; + end + endcase + + // Transmit state machine + case (tx_state) + TX_IDLE: begin + if (transmit) begin + // If the transmit flag is raised in the idle + // state, start transmitting the current content + // of the tx_byte input. + tx_data = tx_byte; + // Send the initial, low pulse of 1 bit period + // to signal the start, followed by the data + tx_clk_divider = CLOCK_DIVIDE; + tx_countdown = 4; + tx_out = 0; + tx_bits_remaining = 8; + tx_state = TX_SENDING; + end + end + TX_SENDING: begin + if (!tx_countdown) begin + if (tx_bits_remaining) begin + tx_bits_remaining = tx_bits_remaining - 1; + tx_out = tx_data[0]; + tx_data = {1'b0, tx_data[7:1]}; + tx_countdown = 4; + tx_state = TX_SENDING; + end else begin + // Set delay to send out 2 stop bits. + tx_out = 1; + tx_countdown = 8; + tx_state = TX_DELAY_RESTART; + end + end + end + TX_DELAY_RESTART: begin + // Wait until tx_countdown reaches the end before + // we send another transmission. This covers the + // "stop bit" delay. + tx_state = tx_countdown ? TX_DELAY_RESTART : TX_IDLE; + end + endcase +end + +endmodule diff --git a/yosys-sim-script b/yosys-sim-script new file mode 100755 index 0000000..eae3049 --- /dev/null +++ b/yosys-sim-script @@ -0,0 +1,3 @@ +read_verilog -sv flash.v +prep -top top -nordff +sim -clock CLK -vcd test.vcd -n 200 -- 2.39.2