use Data::SExpression qw/consp scalarp/;
use Scalar::Util qw/looks_like_number/;
-our $VERSION = '0.001001';
+our $VERSION = '0.004';
our %TYPES = (
LIST => 0,
CONS => 3,
ATOM => 4,
PROGN => 5,
- MAKELIST => 6,
+ 'REVERSE-LIST' => 6,
FUNCALL => 7,
);
$addr = $self->process($addr) if ref $addr eq 'ARRAY';
die 'Addr of toplevel is not atom: ', Dumper($addr), "\n" unless scalarp($addr);
-
my ($comment_type, $comment_addr) = ($type, $addr);
-
- unless (looks_like_number $addr) { # is symbol
- unless (exists $self->{symbols}{$addr}) {
- $self->{symbols}{$addr} = $self->{nsymbols};
- $self->{nsymbols}++;
- }
- $addr = $self->{symbols}{$addr}
- }
-
die 'Computed addr is not a number: ', Dumper($addr), "\n" unless looks_like_number $addr;
- if (ref $type eq 'Data::SExpression::Symbol') {
+ if (!looks_like_number $type) {
die "No such type: $type\n" unless exists $TYPES{$type};
$type = $TYPES{$type};
- } elsif (!looks_like_number $type) {
- die "Type is not a number or symbol: $type\n"
}
+ $addr += (1 << $self->{addr_bits}) if $addr < 0;
die "Type too large: $type\n" unless $type < (1 << $self->{type_bits});
die "Addr too large: $addr\n" unless $addr < (1 << $self->{addr_bits});
my $result = ($type << $self->{addr_bits}) + $addr;
$args{addr_bits} //= 8;
$args{freeptr} //= 6;
$args{memory} //= [0, 0, (1<<$args{addr_bits}), (1<<$args{addr_bits}), 0, 0, 0];
- $args{symbols}{NIL} = 0;
- $args{symbols}{T} = 1;
- $args{nsymbols} = 2;
$args{comment} = ['(cdr part of NIL)', '(car part of NIL)', '(cdr part of T)', '(car part of T)', '(free storage pointer)', '', '(result of computation)'];
bless \%args, $class
}
-sub print {
+sub print_binary16 {
my ($self, $fh) = @_;
- $fh //= \*STDOUT;
+ $fh //= \*STDOUT; # uncoverable condition right
+
+ die "addr_bits + type_bits >= 16\n"if $self->{addr_bits} + $self->{type_bits} > 16;
+
+ my $length = @{$self->{memory}};
+ print $fh pack('n', $length);
+ for (@{$self->{memory}}) {
+ print $fh pack('n', $_)
+ }
+}
+
+sub print_verilog {
+ my ($self, $fh) = @_;
+ $fh //= \*STDOUT; # uncoverable condition right
my $bits = $self->{type_bits} + $self->{addr_bits};
my $index_length = length $#{$self->{memory}};
}
my $spaces = ' ' x ($bits + 5 - (length $val));
$index = sprintf $index_format, $index;
- say $fh "mem[$index] <= $val;$spaces // $comment"
+
+ print $fh "mem[$index] <= $val;";
+ print $fh "$spaces // $comment" if defined $comment;
+ print $fh "\n";
}
+
+}
+sub parse_and_print_binary16 {
+ my ($self, $string, $fh) = @_;
+ $self->parse($string);
+ $self->finish;
+ $self->print_binary16($fh);
}
-sub parse_and_print {
+sub parse_and_print_verilog {
my ($self, $string, $fh) = @_;
$self->parse($string);
$self->finish;
- $self->print($fh);
+ $self->print_verilog($fh);
}
1;
use App::Scheme79asm;
my $asm = App::Scheme79asm->new(type_bits => 3, addr_bits => 5);
- $asm->parse_and_print('(number 70)');
+ $asm->parse_and_print_verilog('(number 70)');
=head1 DESCRIPTION
format. This module takes a string containing a sequence of
S-expressions. Each S-expression is a list of one of three types:
-C<(tag value)>, for example C<(symbol nil)>, represents a value to be
+C<(tag value)>, for example C<(symbol 2)>, represents a value to be
put in memory (for example a number, or a symbol, or a variable
reference).
In normal use a single S-expression will be supplied, representing an
entire program.
-The B<parse_and_print> method takes such a string and prints a block
-of verilog code assigning the memory contents to an array named
-C<mem>.
+The C<tag> is either a number, a type, or a primitive.
+The available types are:
+
+=over
+
+=item LIST
+
+=item SYMBOL (syn. NUMBER)
+
+=item VAR (syn. VARIABLE)
+
+=item CLOSURE
+
+=item PROC (syn. PROCEDURE)
+
+=item IF (syn. COND, CONDITIONAL)
+
+=item CALL
+
+=item QUOTE (syn. QUOTED)
+
+=back
+
+The available primitives are:
+
+=over
+
+=item MORE
+
+=item CAR
+
+=item CDR
+
+=item CONS
+
+=item ATOM
+
+=item PROGN
+
+=item REVERSE-LIST
+
+=item FUNCALL
+
+=back
+
+The following methods are available:
+
+=over
+
+=item App::Scheme79asm->B<new>([key => value, key => value, ...])
+
+Create a new assembler object. Takes a list of keys and values, here
+are the possible keys:
+
+=over
+
+=item type_bits
+
+=item address_bits
+
+A word is made of a type and an address, with the type occupying the
+most significant C<type_bits> (default 3) bits, and the address
+occupying the least significant C<address_bits> (default 8) bits.
+Therefore the word size is C<type_bits + address_bits> (default 13).
+
+=item freeptr
+
+A pointer to the last used byte in memory (default 6). The program
+will be laid out starting with location C<freeptr + 1>.
+
+=item memory
+
+The initial contents of the memory. Note that locations 4, 5, 6 will
+be overwritten, as will every location larger than the value of
+C<freeptr>.
+
+=item comment
+
+The initial comments for memory entries. C<< $comment->[$i] >> is the
+comment for C<< $memory->[$i] >>.
+
+=back
+
+=item $asm->B<parse>(I<$string>)
+
+Parse a sequence of S-expressions and lay it out in memory.
+Can be called multiple times to lay out multiple sequences of
+S-expressions one after another.
+
+=item $asm->B<process>(I<$sexp>)
+
+Given an already-parsed sexp (meaning a
+L<Data::SExpression> object), lay it out in memory.
+Can be called multiple times to lay out multiple sequences of
+S-expressions one after another.
+
+=item $asm->B<finish>
+
+Move the last pointer to position 5, and put the free pointer at
+position 4. After all sequences of S-expressions have been given to
+B<parse>, this method should be called.
+
+=item $asm->B<print_binary16>([I<$fh>])
+
+Print the length of the memory (as a big-endian 16-bit value),
+followed by the memory contents as a sequence of big-endian 16-bit
+values to the given filehandle (default STDOUT). Dies if
+C<addr_bits + type_bits> is more than 16.
+
+Big-endian 16-bit values can be decoded with C<unpack 'n', $value>.
+
+=item $asm->B<print_verilog>([I<$fh>])
+
+Print a block of Verilog code assigning the memory contents to an
+array named C<mem> to the given filehandle (default STDOUT).
+
+=item $asm->B<parse_and_print_binary16>(I<$string>[, I<$fh>])
+
+Convenience method that calls B<parse>($string), B<finish>, and then
+B<print_binary16>($fh).
+
+=item $asm->B<parse_and_print_verilog>(I<$string>[, I<$fh>])
+
+Convenience method that calls B<parse>($string), B<finish>, and then
+B<print_verilog>($fh).
-More documentation and features to follow.
+=back
=head1 SEE ALSO
projects / app-scheme79asm.git / blobdiff