Proper macros for simulation/normal running

[clump.git] / lisp_processor.v

`include "asciihex.v"
`include "generic_fifo_sc_a.v"
`include "gc.v"
`include "eval.v"
`include "ram.v"
`include "rom.v"
`include "prescaler.v"
`include "single_trigger.v"
`include "uart.v"

`define GCOP_NOP      4'd0
`define GCOP_CDR      4'd1
`define GCOP_CAR      4'd2
`define GCOP_CDRQ     4'd3
`define GCOP_CARQ     4'd4
`define GCOP_CARR     4'd5
`define GCOP_CDRRX    4'd6
`define GCOP_CARRX    4'd7
`define GCOP_CDRQX    4'd8
`define GCOP_CONS     4'd9
`define GCOP_XCONS    4'd10
`define GCOP_RPLACDR  4'd11
`define GCOP_LDQ      4'd12
`define GCOP_RDQ      4'd13
`define GCOP_RDQA     4'd14
`define GCOP_RDQCDRRX 4'd15

module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
   wire [15:0] result;

   reg [5:0]   initial_reset = 30;
   always @ (posedge clk)
	 if (initial_reset) initial_reset <= initial_reset - 1;

   reg [1:0]  counter = 0;

   wire gc_clock = counter[1] & !initial_reset;
   wire eval_clock = !counter[1] & step_eval & !initial_reset;

   always @ (posedge clk)
	 counter <= counter + 1;

   wire [15:0] E1;
   wire [15:0] E2;
   wire [3:0] gcop;
   wire [5:0] gostate;
   wire [5:0] eostate;
   wire 	  conn_ea;
   wire 	  conn_et;

   wire 	  step_eval;

   GC gc (.clk(gc_clock), .mclk(clk), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .result(result));

   EVAL eval (.clk(eval_clock), .mclk(clk), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));

   // UART outputs
   wire       uart_rx_signal;
   wire [7:0] uart_rx_byte;
   wire       uart_is_receiving;
   wire       uart_is_transmitting;
   wire       uart_rx_error;

   // Input logic
   wire [3:0] fifo_in;
   wire [3:0] fifo_out;
   wire 	  fifo_full;
   wire 	  fifo_empty;
   wire 	  fifo_re = 0;//eval_clock & inst == `INST_READ & !fifo_empty;
   wire 	  fifo_we = uart_rx_signal & !fifo_full;

   ascii_to_hex a2h (.ascii({1'b0, uart_rx_byte[6:0]}), .hex(fifo_in));

   generic_fifo_sc_a #(.dw(4), .aw(4)) fifo
    (.clk(clk),
     .rst(1'b1),
     .re(fifo_re),
     .we(fifo_we),
     .din(fifo_in),
     .dout(fifo_out),
     .full(fifo_full),
     .empty(fifo_empty));

   // UART logic
   reg       uart_tx_signal = 1;
   wire [7:0] uart_tx_byte = result[7:0];

   // 300 baud uart
   uart #(.CLOCK_DIVIDE(39)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));

   // Assign the outputs
   assign led[0] = eval_clock;
   assign led[1] = uart_is_transmitting;
   assign led[2] = uart_is_receiving;
   assign led[3] = recv_error;
endmodule