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3b542afc MG |
1 | `include "master_rom.v" |
2 | ||
3 | `ifdef SIM | |
4 | `define UART_DIVIDE 1 | |
5 | `else | |
6 | `define UART_DIVIDE 1 | |
7 | // s/192/3/ for 19200 baud uart | |
8 | `endif | |
9 | ||
10 | module master(input CLKin, output [4:0] led, output uart_tx, input uart_rx, output reg ready_out = 1, input ready_in); | |
11 | wire clk; | |
12 | wire clk_tmp; | |
13 | ||
14 | //pll pll (.clock_in(CLKin), .clock_out(clk)); | |
15 | ||
16 | reg [20:0] counter = 0; | |
17 | ||
18 | reg clk = 0; | |
19 | ||
20 | always @ (posedge CLKin) begin | |
21 | if(counter == 5000) begin | |
22 | counter <= 0; | |
23 | clk <= 1 - clk; | |
24 | end | |
25 | else | |
26 | counter <= counter + 1; | |
27 | end | |
28 | ||
7f1b6bd9 MG |
29 | reg [3:0] program_counter = 0; |
30 | wire [31:0] rom_output; | |
3b542afc MG |
31 | |
32 | master_rom master_rom (.clk(clk), .addr(program_counter), .data(rom_output)); | |
33 | ||
34 | ||
35 | `define STATE_SEND 0 | |
36 | `define STATE_WAIT_PROPAGATE 1 | |
37 | `define STATE_WAIT_NEWS 2 | |
7f1b6bd9 MG |
38 | `define STATE_PROPAGATE_NEWS 3 |
39 | `define STATE_WASTE_TIME 4 | |
3b542afc MG |
40 | |
41 | reg [5:0] state = `STATE_SEND; | |
42 | reg [5:0] uart_ptr = 0; | |
43 | ||
44 | wire received; | |
45 | wire [7:0] rx_byte; | |
46 | reg transmit = 0; | |
47 | reg [7:0] tx_byte = 0; | |
48 | wire is_receiving; | |
49 | wire is_transmitting; | |
50 | ||
51 | // 19200 (actually 300) baud uart | |
52 | uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .received(received), .transmit(transmit), .tx_byte(tx_byte), .rx_byte(rx_byte), .is_receiving(is_receiving), .is_transmitting(is_transmitting)); | |
53 | ||
7f1b6bd9 MG |
54 | reg [15:0] waste_counter = 0; |
55 | ||
56 | reg [7:0] saved_news [3:0]; | |
57 | ||
58 | assign led[4] = state != `STATE_WASTE_TIME; | |
59 | assign led[3:0] = 0; | |
60 | ||
3b542afc MG |
61 | always @(posedge clk) begin |
62 | case(state) | |
63 | `STATE_SEND: begin | |
64 | if(transmit) begin | |
65 | transmit <= 0; | |
66 | end else if(uart_ptr == 4) begin | |
67 | program_counter <= program_counter + 1; | |
68 | uart_ptr <= 0; | |
7f1b6bd9 MG |
69 | if(rom_output[26:24] == 6) // `OP_ROUTE |
70 | state <= `STATE_WAIT_NEWS; | |
71 | else | |
72 | state <= `STATE_WAIT_PROPAGATE; | |
3b542afc MG |
73 | end else if(!is_transmitting && ready_in) begin |
74 | tx_byte <= rom_output[uart_ptr * 8 +: 8]; | |
75 | transmit <= 1; | |
76 | uart_ptr <= uart_ptr + 1; | |
77 | end | |
78 | end | |
79 | ||
80 | `STATE_WAIT_PROPAGATE: begin | |
81 | if(received) begin | |
7f1b6bd9 | 82 | state <= `STATE_WASTE_TIME; |
3b542afc MG |
83 | end |
84 | end | |
85 | ||
7f1b6bd9 MG |
86 | `STATE_WASTE_TIME: begin |
87 | if(waste_counter == 100) begin | |
88 | waste_counter <= 0; | |
89 | state <= `STATE_SEND; | |
90 | end else | |
91 | waste_counter <= waste_counter + 1; | |
92 | end | |
93 | ||
3b542afc | 94 | `STATE_WAIT_NEWS: begin |
7f1b6bd9 MG |
95 | /** On a route instruction, we: |
96 | - receive the instruction back | |
97 | - receive the news | |
98 | - propagate the news | |
99 | - go back to `STATE_SEND | |
100 | */ | |
101 | if(uart_ptr == 8) begin | |
102 | state <= `STATE_PROPAGATE_NEWS; | |
103 | uart_ptr <= 0; | |
104 | end else if(received) begin | |
105 | if(uart_ptr[2]) /* uart_ptr >= 4 */ | |
106 | saved_news[uart_ptr[1:0]] <= rx_byte; | |
107 | uart_ptr <= uart_ptr + 1; | |
108 | end | |
109 | end // case: `STATE_WAIT_NEWS | |
3b542afc | 110 | |
7f1b6bd9 MG |
111 | `STATE_PROPAGATE_NEWS: begin |
112 | if(uart_ptr == 4) begin | |
113 | state <= `STATE_WASTE_TIME; | |
114 | uart_ptr <= 0; | |
115 | end else if(!is_transmitting && ready_in) begin | |
116 | tx_byte <= saved_news[uart_ptr]; | |
117 | transmit <= 1; | |
118 | uart_ptr <= uart_ptr + 1; | |
119 | end | |
3b542afc MG |
120 | end |
121 | endcase | |
122 | end | |
123 | ||
124 | endmodule |