[clump.git] / master_rom.v

// ROM module with single input addr, output port, and clock input.
// Data is clocked out of the ROM on positive clock edges.

module master_rom (input clk, input [7:0] addr, output reg [31:0] data);
   reg [31:0] rom [0:255];
   initial $readmemh("code.hex", rom);

   always @ (posedge clk) begin
	  data <= rom[addr];
   end
endmodule
Commit	Line	Data
3b542afc MG	1	// ROM module with single input addr, output port, and clock input.
	2	// Data is clocked out of the ROM on positive clock edges.
	3
46a95fd3 MG	4	module master_rom (input clk, input [7:0] addr, output reg [31:0] data);
	5	reg [31:0] rom [0:255];
	6	initial $readmemh("code.hex", rom);
	7
3b542afc	8	always @ (posedge clk) begin
46a95fd3	9	data <= rom[addr];
3b542afc MG	10	end
3b542afc MG	11	endmodule