Add diagrams and pictures
[clump.git] / Makefile
... / ...
CommitLineData
1DEVICE = hx1k
2
3all: toplevel.bin
4
5toplevel.bin: master.rpt master.bin worker.rpt worker.bin
6 tools/icestorm/icemulti/icemulti -o toplevel.bin -v -p0 worker.bin master.bin
7
8master.blif: master.v
9 tools/yosys/yosys -p 'synth_ice40 -top master -blif $@' $<
10
11worker.blif: worker.v
12 tools/yosys/yosys -p 'synth_ice40 -top worker -blif $@' $<
13
14%.asc: %.pcf %.blif
15 tools/arachne-pnr/bin/arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P tq144 -s 4
16
17%.bin: %.asc
18 tools/icestorm/icepack/icepack $< $@
19
20%.rpt: %.asc
21 tools/icestorm/icetime/icetime -C tools/icestorm/icebox/chipdb-$(subst hx,,$(subst lp,,$(DEVICE))).txt -d $(DEVICE) -mtr $@ $<
22
23prog: toplevel.bin
24 tools/icestorm/iceprog/iceprog $<
25
26progall: toplevel.bin
27 bash progall.sh
28
29progmaster: master.bin
30 tools/icestorm/iceprog/iceprog $<
31
32clean:
33 rm -f master.blif master.asc worker.blif worker.asc master.bin worker.bin toplevel.bin
34
35
36sim:
37 tools/yosys/yosys -p 'read_verilog -sv -DSIM worker.v; prep -top worker -nordff; sim -clock CLKin -vcd test.vcd -n 3000'
38
39.PHONY: all prog clean sim
This page took 0.008195 seconds and 4 git commands to generate.