| 1 | module GCRAM |
| 2 | (input clk, input we, input[12:0] addr, input[15:0] di, output reg [15:0] do); |
| 3 | reg [15:0] mem [4095:0]; |
| 4 | |
| 5 | always @ (negedge clk) |
| 6 | do <= #1 mem[addr]; |
| 7 | |
| 8 | always @ (negedge clk) |
| 9 | if (we) |
| 10 | mem[addr] <= #1 di; |
| 11 | |
| 12 | initial begin |
| 13 | mem[ 0] <= 0; // (cdr part of NIL) |
| 14 | mem[ 1] <= 0; // (car part of NIL) |
| 15 | mem[ 2] <= 16'b0010000000000000; // (cdr part of T) |
| 16 | mem[ 3] <= 16'b0010000000000000; // (car part of T) |
| 17 | mem[ 4] <= 16'd12; // (free storage pointer) |
| 18 | mem[ 5] <= 16'b1100000000000111; // CALL 7 |
| 19 | mem[ 6] <= 0; // (result of computation) |
| 20 | mem[ 7] <= 16'b0000000000001001; // MORE 9 |
| 21 | mem[ 8] <= 16'b0010000000000101; // NUMBER 5 |
| 22 | mem[ 9] <= 16'b1110000000000000; // FUNCALL NIL |
| 23 | mem[10] <= 16'b1000000000001011; // PROC 11 |
| 24 | mem[11] <= 16'b0101111111111110; // VAR -2 |
| 25 | end |
| 26 | endmodule |