module GC (input clk, input mclk, input [7:0] Ein, output [7:0] Eout, input [3:0] gcop, output [5:0] ostate, output step_eval);
   reg [5:0] gostate = 6'o2;
   reg [5:0] gnstate;
   reg [16:0] rom_output;
   reg [7:0]  Ein_latched;

   always @(posedge clk) begin
	  Ein_latched <= Ein;
   end

   wire ga_zero_disp = rom_output[15];
   wire gcop_disp    = rom_output[14];
   wire write        = rom_output[13];
   wire adr          = rom_output[12];
   wire rdR          = rom_output[11];
   wire rdQ          = rom_output[10];
   wire rdP_plus     = rom_output[9];
   wire rdP          = rom_output[8];
   wire ldS          = rom_output[7];
   wire ldR          = rom_output[6];
   wire ldQ          = rom_output[5];
   wire ldP          = rom_output[4];
   wire conn_i       = rom_output[3];
   wire conn_et      = rom_output[2];
   wire conn_ea      = rom_output[1];
   assign step_eval  = rom_output[0];

   wire ga_zero = ~|G[7:5];

   always @* begin
	  case(gostate)
		6'o00:   begin rom_output <= 16'o010242; gnstate <= 6'o01; end
		6'o01:   begin rom_output <= 16'o000031; gnstate <= 6'o02; end
		6'o02:   begin rom_output <= 16'o040000; gnstate <= 6'o20; end
		6'o03:   begin rom_output <= 16'o000126; gnstate <= 6'o04; end
		6'o04:   begin rom_output <= 16'o001200; gnstate <= 6'o05; end
		6'o05:   begin rom_output <= 16'o002020; gnstate <= 6'o06; end
		6'o06:   begin rom_output <= 16'o000051; gnstate <= 6'o02; end
		6'o07:   begin rom_output <= 16'o002020; gnstate <= 6'o10; end
		6'o10:   begin rom_output <= 16'o001200; gnstate <= 6'o11; end
		6'o11:   begin rom_output <= 16'o004020; gnstate <= 6'o12; end
		6'o12:   begin rom_output <= 16'o002100; gnstate <= 6'o13; end
		6'o13:   begin rom_output <= 16'o000057; gnstate <= 6'o02; end
		6'o14:   begin rom_output <= 16'o004020; gnstate <= 6'o04; end
		6'o15:   begin rom_output <= 16'o000246; gnstate <= 6'o16; end
		6'o16:   begin rom_output <= 16'o020001; gnstate <= 6'o02; end
		6'o17:   begin rom_output <= 16'o002100; gnstate <= 6'o42; end
		6'o20:   begin rom_output <= 16'o000001; gnstate <= 6'o02; end
		6'o21:   begin rom_output <= 16'o010306; gnstate <= 6'o06; end
		6'o22:   begin rom_output <= 16'o000440; gnstate <= 6'o03; end
		6'o23:   begin rom_output <= 16'o012200; gnstate <= 6'o12; end
		6'o24:   begin rom_output <= 16'o000500; gnstate <= 6'o07; end
		6'o25:   begin rom_output <= 16'o004040; gnstate <= 6'o24; end
		6'o26:   begin rom_output <= 16'o014200; gnstate <= 6'o06; end
		6'o27:   begin rom_output <= 16'o000440; gnstate <= 6'o14; end
		6'o30:   begin rom_output <= 16'o012300; gnstate <= 6'o06; end
		6'o31:   begin rom_output <= 16'o111300; gnstate <= 6'o44; end
		6'o32:   begin rom_output <= 16'o111300; gnstate <= 6'o40; end
		6'o33:   begin rom_output <= 16'o014200; gnstate <= 6'o15; end
		6'o34:   begin rom_output <= 16'o000047; gnstate <= 6'o02; end
		6'o35:   begin rom_output <= 16'o002007; gnstate <= 6'o02; end
		6'o36:   begin rom_output <= 16'o002003; gnstate <= 6'o02; end
		6'o37:   begin rom_output <= 16'o014200; gnstate <= 6'o55; end
		6'o40:   begin rom_output <= 16'o004020; gnstate <= 6'o17; end
		6'o41:   begin rom_output <= 16'o000000; gnstate <= 6'o41; end
		6'o42:   begin rom_output <= 16'o000206; gnstate <= 6'o47; end
		6'o43:   begin rom_output <= 16'o000106; gnstate <= 6'o46; end
		6'o44:   begin rom_output <= 16'o004020; gnstate <= 6'o43; end
		6'o45:   begin rom_output <= 16'o000000; gnstate <= 6'o41; end
		6'o46:   begin rom_output <= 16'o002200; gnstate <= 6'o47; end
		6'o47:   begin rom_output <= 16'o020440; gnstate <= 6'o50; end
		6'o50:   begin rom_output <= 16'o111200; gnstate <= 6'o52; end
		6'o51:   begin rom_output <= 16'o021100; gnstate <= 6'o54; end
		6'o52:   begin rom_output <= 16'o004200; gnstate <= 6'o51; end
		6'o53:   begin rom_output <= 16'o000000; gnstate <= 6'o41; end
		6'o54:   begin rom_output <= 16'o004021; gnstate <= 6'o02; end
		6'o55:   begin rom_output <= 16'o002100; gnstate <= 6'o56; end
		6'o56:   begin rom_output <= 16'o000050; gnstate <= 6'o57; end
		6'o57:   begin rom_output <= 16'o004007; gnstate <= 6'o02; end
		default: begin rom_output <= 16'o040000; gnstate <= 6'o20; end
	  endcase; // case (gostate)
   end // always @ (posedge mclk)

   always @ (posedge clk) begin
	  gostate <=
			   /* 				ga_zero_disp ? (gnstate | ga_zero) : */
				gcop_disp ? (gnstate | gcop) :
				gnstate;
   end // always @ (posedge clk)

   assign ostate = gostate;

   reg [4:0] P = 5'b0; // free storage pointer begins at 0
   reg [7:0] Q;
   reg [7:0] R;
   reg [7:0] S;

   reg [4:0] A; // latched address

   wire [7:0] I;

   wire [7:0] G;

   /*
   assign G = rdR ? R : 8'bzzzzzzzz;
   assign G = rdQ ? Q : 8'bzzzzzzzz;
   assign G = rdP ? {3'b0, P} : 8'bzzzzzzzz;
   assign G = rdP_plus ? {3'b0, P+1} : 8'bzzzzzzzz;
   assign G = conn_i ? I : 8'bzzzzzzzz;
   assign G[4:0] = conn_ea ? E[4:0] : 5'bzzzzz;
   assign G[7:5] = conn_et ? E[7:5] : 3'bzzz;

   assign E[4:0] = conn_ea ? G[4:0] : 5'bzzzzz;
   assign E[7:5] = conn_et ? G[7:5] : 3'bzzz;
	*/

   wire [7:0] GfromR = rdR ? R : 0;
   wire [7:0] GfromQ = rdQ ? Q : 0;
   wire [7:0] GfromP = rdP ? {3'b0, P} : 0;
   wire [7:0] GfromP_plus = rdP_plus ? {3'b0, P + 1} : 0;
   wire [7:0] GfromI = conn_i ? I : 0;
   wire [4:0] GAfromE = conn_ea ? Ein_latched[4:0] : 0;
   wire [3:0] GTfromE = conn_et ? Ein_latched[7:5] : 0;
   wire [7:0] GfromE = {GTfromE, GAfromE};

   assign G = GfromR | GfromQ | GfromP | GfromP_plus | GfromI | GfromE;

   assign Eout[4:0] = conn_ea ? G[4:0] : 0;
   assign Eout[7:5] = conn_et ? G[7:5] : 0;

   generic_dpram #(.aw(5), .dw(8)) RAM
	 ( .rclk(mclk),
	   .wclk(mclk),
	   .rrst(1'b0),
	   .wrst(1'b0),
	   .rce(1'b1),
	   .wce(1'b1),

	   .oe(1'b1),
	   .we(write),
	   .raddr(A),
	   .waddr(A),
	   .do(I),
	   .di(S));

   always @ (posedge clk) begin
	  if (ldS) S = G;
	  if (ldP) P <= G[4:0];
	  if (ldR) R <= G;
	  if (ldQ) Q <= G;
	  if (adr) A <= S[4:0];
   end
endmodule // GC