`include "master_rom.v"

`ifdef SIM
 `define UART_DIVIDE 1
`else
 `define UART_DIVIDE 1
 // s/192/3/ for 19200 baud uart
`endif

module master(input CLKin, output [4:0] led, output uart_tx, input uart_rx, output reg ready_out = 1, input ready_in);
   wire clk;
   wire clk_tmp;

   //pll pll (.clock_in(CLKin), .clock_out(clk));

   reg [20:0] counter = 0;

   reg 		  clk = 0;

   always @ (posedge CLKin) begin
	  if(counter == 5000) begin
		 counter <= 0;
		 clk <= 1 - clk;
	  end
	  else
		counter <= counter + 1;
   end

   reg [4:0] program_counter = 0;
   wire [63:0] rom_output;

   master_rom master_rom (.clk(clk), .addr(program_counter), .data(rom_output));


`define STATE_SEND 0
`define STATE_WAIT_PROPAGATE 1
`define STATE_WAIT_NEWS 2

   reg [5:0] state = `STATE_SEND;
   reg [5:0] uart_ptr = 0;

   wire 	   received;
   wire [7:0]  rx_byte;
   reg 		   transmit = 0;
   reg  [7:0]  tx_byte = 0;
   wire 	   is_receiving;
   wire 	   is_transmitting;

   // 19200 (actually 300) baud uart
   uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .received(received), .transmit(transmit), .tx_byte(tx_byte), .rx_byte(rx_byte), .is_receiving(is_receiving), .is_transmitting(is_transmitting));

   always @(posedge clk) begin
	  case(state)
		`STATE_SEND: begin
		   if(transmit) begin
			  transmit <= 0;
		   end else if(uart_ptr == 4) begin
			  program_counter <= program_counter + 1;
			  uart_ptr <= 0;
			  state <= `STATE_WAIT_PROPAGATE;
		   end else if(!is_transmitting && ready_in) begin
			  tx_byte <= rom_output[uart_ptr * 8 +: 8];
			  transmit <= 1;
			  uart_ptr <= uart_ptr + 1;
		   end
		end

		`STATE_WAIT_PROPAGATE: begin
		   if(received) begin
			  state <= `STATE_SEND;
		   end
		end

		`STATE_WAIT_NEWS: begin

		end
	  endcase
   end

endmodule