// ROM module with single input addr, output port, and clock input.
// Data is clocked out of the ROM on positive clock edges.

module master_rom (input clk, input [3:0] addr, output reg [31:0] data);
   always @ (posedge clk) begin
      case(addr)
0: data <= 32'h04000004;
1: data <= 32'h04010002;
2: data <= 32'h07010010;
3: data <= 32'h00000000;
4: data <= 32'h00000000;
5: data <= 32'h06000001;
6: data <= 32'h07010010;
7: data <= 32'h00000000;
8: data <= 32'h00000000;
9: data <= 32'h04010003;
10: data <= 32'h07010010;
11: data <= 32'h00000000;
12: data <= 32'h00000000;
13: data <= 32'h06000001;
14: data <= 32'h07010010;
15: data <= 32'h00000000;
	  endcase
   end
endmodule