`define STATE_IDLE    2'd0
`define STATE_LENGTH  2'd1
`define STATE_READ1   2'd2
`define STATE_READ2   2'd3

module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output reg finished = 0, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
   reg [1:0] state = `STATE_IDLE;

   reg [12:0] words_left;
   reg [12:0] current_index;

   assign ram_addr = current_index;

   always @ (posedge clk)
	 if (clk_enable) begin
		if(!rx_signal) ram_we <= 0;

		case(state)
		  `STATE_IDLE: begin
			 if(rx_signal) begin
				words_left[12:8] <= rx_byte[4:0];
				words_left[7:0] <= 0;
				current_index <= -1;
				state <= `STATE_LENGTH;
			 end
		  end

		  `STATE_LENGTH: begin
			 if(rx_signal) begin
				words_left[7:0] <= rx_byte;
				state <= `STATE_READ1;
			 end
		  end

		  `STATE_READ1: begin
			 if(rx_signal) begin
				ram_di[15:8] <= rx_byte;
				current_index <= current_index + 1;
				words_left <= words_left - 1;
				state <= `STATE_READ2;
			 end
		  end

		  `STATE_READ2: begin
			 if(rx_signal) begin
				ram_di[7:0] <= rx_byte;
				ram_we <= 1;
				if(|words_left) begin
				   state <= `STATE_READ1;
				end else begin
				   state <= `STATE_IDLE;
				   finished <= 1;
				end
			 end
		  end
		endcase
	 end // if (clk_enable)
	 else
	   finished <= 0;
endmodule