`define STATE_START        2'b00
`define STATE_WRITE1       2'b01
`define STATE_WRITE2       2'b10
`define STATE_INCREMENT    2'b11

module WRITER (input clk, input clk_enable, output reg [7:0] tx_byte, output reg tx_signal = 0, input tx_busy, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] freeptr);
   reg [1:0] state = `STATE_START;

   reg [12:0] current_index;

   assign ram_addr = current_index;

   always @ (posedge clk) begin
	 if (clk_enable) begin
		if(tx_signal)
		  tx_signal <= 0;

		case(state)
		  `STATE_START: begin
			 current_index <= 4;
			 state <= `STATE_WRITE1;
		  end

		  `STATE_WRITE1: begin
			 if(!tx_busy && !tx_signal) begin
				tx_signal <= 1;
				tx_byte <= ram_do[15:8];
				state <= `STATE_WRITE2;
			 end
		  end

		  `STATE_WRITE2: begin
			 if(!tx_busy && !tx_signal) begin
				tx_signal <= 1;
				tx_byte <= ram_do[7:0];
				state <= `STATE_INCREMENT;
			 end
		  end

		  `STATE_INCREMENT: begin
			 current_index <= current_index + 1;
			 if(current_index >= freeptr) begin
				finished <= 1;
				state <= `STATE_START;
			 end else begin
				state <= `STATE_WRITE1;
			 end
		  end
		endcase // case (state)
	 end // if (clk_enable)
	 else
	   finished <= 0;
   end
endmodule