-PROJ = toplevel
-PIN_DEF = toplevel.pcf
+PROJ = master
+PIN_DEF = master.pcf
DEVICE = hx1k
all: $(PROJ).rpt $(PROJ).bin
%.blif: %.v
- tools/yosys/yosys -p 'synth_ice40 -top toplevel -blif $@' $<
+ tools/yosys/yosys -p 'synth_ice40 -top master -blif $@' $<
%.asc: $(PIN_DEF) %.blif
tools/arachne-pnr/bin/arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P tq144
sim:
- tools/yosys/yosys -p 'read_verilog -sv -DSIM toplevel.v; prep -top toplevel -nordff; sim -clock CLKin -vcd test.vcd -n 3000'
+ tools/yosys/yosys -p 'read_verilog -sv -DSIM master.v; prep -top master -nordff; sim -clock CLKin -vcd test.vcd -n 3000'
.PHONY: all prog clean sim