-module EVAL(input clk, input clk_enable, input [15:0] Ein, output [15:0] Eout, output [3:0] gcop, output [5:0] ostate, input conn_ea, input conn_et);
+module EVAL(input clk, input clk_enable, input rst, input [15:0] Ein, output [15:0] Eout, output [3:0] gcop, output [5:0] ostate, input conn_ea, input conn_et);
reg [21:0] rom_output;
- reg [5:0] eostate = 6'o0;
+ reg [5:0] eostate;
reg [5:0] enstate;
reg [15:0] Ein_latched;
wire ldN = rom_output[9];
wire ldX = rom_output[8];
wire ldV = rom_output[7];
- wire [3:0] gcop = rom_output[6:3];
+ assign gcop = rom_output[6:3];
wire [2:0] lit = rom_output[2:0];
wire et_zero = ~|E[15:13];
end // always @ *
always @ (posedge clk) begin
+ if (rst)
+ eostate = 0;
if (clk_enable) begin
eostate <=
et_disp ? (enstate | E[15:13]) :